DS90CR218A_06 Datasheet, PDF (6/11 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

AC Timing Diagrams (Continued)
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FIGURE 5. DS9OCR218A (Receiver) Phase Lock Loop Set Time
FIGURE 6. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
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FIGURE 7. Receiver Powerdown Delay
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