DS90CR217_06 Datasheet, PDF (8/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz

AC Timing Diagrams (Continued)
FIGURE 10. Transmitter LVDS Output Pulse Position Measurement
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Applications Information
DS90CR217 Pin Descriptions — Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I
21 TTL level input.
O
3 Positive LVDS differential data output.
O
3 Negative LVDS differential data output.
I
1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See
Applications Information section.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power
down. See Applications Information section.
I
4 Power supply pins for TTL inputs.
I
5 Ground pins for TTL inputs.
I
1 Power supply pins for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For
example, for lower data rate (clock rate) and shorter cable
lengths (< 2m), the media electrical performance is less
critical. For higher speed/long distance applications the me-
dia’s performance becomes more critical. Certain cable con-
structions provide tighter skew (matched electrical length
between the conductors and pairs). Twin-coax for example,
has been demonstrated at distances as great as 5 meters
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