DS90CR217_06 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz

October 2006
DS90CR217
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link - 85 MHz
General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. At a transmit clock frequency of 85 MHz, 21
bits of TTL data are transmitted at a rate of 595 Mbps per
LVDS data channel. Using a 85 MHz clock, the data through-
put is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is
an ideal means to solve EMI and cable size problems asso-
ciated with wide, high-speed TTL interfaces.
Features
n 20 to 85 MHz shift clock support
n 50% duty cycle on receiver output clock
n Best-in-Class Set & Hold Times on TxINPUTs
n Low power consumption
n ±1V common-mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 1.785 Gbps throughput
n Up to 223 Mbytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
Block Diagram
DS90CR217
Connection Diagrams
Order Number DS90CR217MTD
See NS Package Number MTD48
20190301
DS90CR217
20190321
© 2006 National Semiconductor Corporation DS201903
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