DS90CR217_06 Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz

Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
LLHT
LVDS Low-to-High Transition Time (Figure 2)
LHLT
LVDS High-to-Low Transition Time (Figure 2)
TCIT
TxCLK IN Transition Time (Figure 3)
TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 10)
f = 85 MHz
TPPos1 Transmitter Output Pulse Position for Bit1
TPPos2 Transmitter Output Pulse Position for Bit2
TPPos3 Transmitter Output Pulse Position for Bit3
TPPos4 Transmitter Output Pulse Position for Bit4
TPPos5 Transmitter Output Pulse Position for Bit5
TPPos6 Transmitter Output Pulse Position for Bit6
TCIP
TxCLK IN Period (Figure 5)
TCIH
TxCLK IN High Time (Figure 5)
TCIL
TxCLK IN Low Time (Figure 5)
TSTC
TxIN Setup to TxCLK IN (Figure 5)
f = 85 MHz
THTC
TxIN Hold to TxCLK IN (Figure 5)
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay @ 25˚C, V_CC = 3.3V (Figure 6)
Transmitter Phase Lock Loop Set (Figure 7)
TPDD
Transmitter Powerdown Delay (Figure 9)
TJIT
TxCLK IN Cycle-to-Cycle Jitter
Min
1.0
−0.20
1.48
3.16
4.84
6.52
8.20
9.88
11.76
0.35T
0.35T
2.5
0
3.8
Typ
0.75
0.75
0
1.68
3.36
5.04
6.72
8.40
10.08
T
0.5T
0.5T
Max
1.5
1.5
6.0
0.20
1.88
3.56
5.24
6.92
8.60
10.28
50
0.65T
0.65T
6.3
10
100
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
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