PC87332VLJ Datasheet, PDF (73/98 Pages) National Semiconductor (TI) – PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac

7 0 Parallel Port (Continued)
EPP 1 7 Address Read
The following procedure reads from the address register
See also Figure 7-2
1 The host reads a byte from the EPP address register RD
goes low to gate PD0–7 into D0–7
2 The EPP pulls ASTRB low to signal the peripheral to start
sending data
3 If WAIT is low during the host read cycle then the EPP
pulls IOCHRDY low
When WAIT goes high the EPP stops pulling IOCHRDY
to low
4 When IOCHRDY goes high it causes RD to go high If
WAIT is high during the host read cycle then the EPP
does not pull IOCHRDY to low
5 When RD goes high it causes the EPP to pull ASTRB
high
Only when ASTRB is high can the EPP change PD0 – 7
After ASTRB goes high the EPP pins D0–7 are at TRI-
STATE
2 The EPP first pulls WRITE low and then pulls ASTRB low
to indicate that data has been sent
3 If WAIT is high during the host write cycle ZWS goes low
and IOCHRDY goes high
4 When the host pulls WR high the EPP pulls ASTRB
ZWS and WRITE to high
Only when WRITE and ASTRB are high can the EPP
change PD0 – 7
Note Read operation is similar except for data direction and activation of
RD instead of write
5 If the peripheral is fast enough to pull WAIT low before
the host terminates the write cycle the EPP pulls
IOCHRDY to low but does not pull ZWS to low thus
carrying out a normal (non-ZWS EPP 1 7) write operation
EPP Zero Wait State (ZWS) Data Write Operation
(both 1 7 and 1 9)
EPP 1 7 and 1 9 Zero Wait State data write read operations
are similar to the EPP Zero Wait State address write read
operations with the exception that the data strobe (DSTRB
signal) and a data register replace the address strobe
(ASTRB signal) and the address register respectively See
Figure 7-3
TL C 11930 – 16
FIGURE 7-2 EPP 1 7 Address Read
EPP 1 7 Data Write and Data Read
This procedure writes to the selected peripheral device or
register See also Figure 7-3
An EPP 1 7 data write operation is similar to the EPP 1 7
address write operation and an EPP 1 7 data read opera-
tion is similar to the EPP 1 7 address read operation except
that the data strobe (DSTRB signal) and a data register
replace the address strobe (ASTRB signal) and the address
register respectively
EPP Zero Wait State (ZWS) Address Write Operation
(both 1 7 and 1 9)
The following procedure performs a short write to the se-
lected peripheral device or register
ZWS should be configured as follows bit 5 of FCR is 1 and
bit 6 of FCR is 0
1 The host writes a byte to the EPP address register WR
goes low to latch D0–7 into the data register The latch
drives the data register onto PD0–7
TL C 11930 – 17
FIGURE 7-3 EPP Write with ZWS
EPP 1 9 Address Write
The following procedure selects a peripheral or register
See also Figure 7-4
1 The host writes a byte to the EPP address register
2 The EPP pulls IOCHRDY low and waits for WAIT to go
low
3 When WAIT goes low the EPP pulls WRITE to low and
drives the latched byte onto PD0 – 7
If WAIT was already low then steps 2 and 3 occur con-
currently
4 The EPP pulls ASTRB low and waits for WAIT to go high
5 When WAIT goes high the EPP stops pulling IOCHRDY
low pulls ASTRB high and waits for WAIT to go low
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