PC87332VLJ Datasheet, PDF (61/98 Pages) National Semiconductor (TI) – PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac

5 0 FDC Functional Description (Continued)
5 4 DATA SEPARATOR
The internal data separator is a Fully Digital PLL (FDPLL)
The FDPLL synchronizes the raw data signal read from the
disk drive The synchronized signal is used to separate the
encoded clock and data pulses The data pulses are deseri-
alized into bytes and then sent to the mP by the controller
The FDC supports five data rates 250 kbps 300 kbps
500 kbps 1 Mbps and 2 Mbps
The FDC has a dynamic window margin and lock range per-
formance capable of handling a wide range of floppy disk
drives In addition the data separator operates well under a
variety of conditions including the high motor speed fluctua-
tions of floppy-compatible tape drives
Figure 5-1 shows the floppy disk controller dynamic window
margin performance at the four different data rates Dynam-
ic window margin is the primary indicator of the quality and
performance level of the data separator This measurement
indicates how much motor speed variation (MSV) of the
drive spindle motor and bit jitter (or window margin) can be
tolerated by the data separator
MSV is shown on the x-axis of the dynamic window margin
graph MSV is translated directly to the actual data rate of
the data as it is read from the disk by the data separator
That is a faster than nominal motor results in a higher fre-
quency in the actual data rate
The dynamic window margin performance curves also indi-
cate how much bit jitter (or window margin) can be tolerated
by the data separator This parameter is shown on the
y-axis of the graphs Bit jitter is caused by the magnetic
interaction of adjacent data pulses on the disk which effec-
tively shifts the bits away from their nominal positions in the
middle of the bit window Window margin is commonly mea-
sured as a percentage This percentage indicates how far a
data bit can be shifted early or late with respect to its nomi-
nal bit position and still be read correctly by the data sepa-
rator If the data separator cannot correctly decode a shifted
bit then the data is misread and a CRC error results
The dynamic window margin performance curves contain
two pieces of information
1 the maximum range of MSV (also called ‘‘lock range’’)
that the data separator can handle with no read errors
and
2 the maximum percentage of window margin (or bit jitter)
that the data separator can handle with no read errors
Thus the area under the dynamic window margin curves in
Figure 5-1 is the range of MSV and bit jitter that the FDC
can handle with no read errors The FDC internal digital data
separator has a much better performance than comparable
digital data separator designs and does not require any ex-
ternal components
Note The dynamic window margin curves were generated using a FlexStar
FS-540 Floppy Disk Simulator and a proprietary dynamic window mar-
gin test program written by National Semiconductor
The controller takes best advantage of the internal digital
data separator by implementing a sophisticated read algo-
rithm
This ID search algorithm shown in Figure 5-2 enhances the
FDPLL’s lock characteristics by forcing the FDPLL to relock
to the crystal reference frequency any time the data separa-
tor attempts to lock to a non-preamble pattern This algo-
rithm ensures that the FDPLL is not thrown way out of lock
by write splices or bad data fields
250 300 500 kbps and 1 Mbps
TL C 11930 – 8
FIGURE 5-1 PC87332 Dynamic Window Margin Performance
(Typical Performance at V_DD e 5 0V 25 C)
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