PC87332VLJ Datasheet, PDF (17/98 Pages) National Semiconductor (TI) – PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac

2 0 Configuration Registers
2 1 OVERVIEW
Eight registers constitute the Base Configuration Register
set and control the PC87332 set-up In general these reg-
isters control the enabling of major functions (FDC UARTs
parallel port pin functionality etc ) the I O addresses of
these functions and whether they power-down via hard-
ware control or not These registers are the Function Enable
Register (FER) Function Address Register (FAR) Power
and Test Register (PTR) Function Control Register (FCR)
the Printer Control Register (PCR) the Power Management
Control Register (PMC) the Tape UARTs and Parallel Port
Configuration Register (TUP) and the SuperI O (SIO) Iden-
tification Register (SID)
During reset the PC87332 loads a set of default values se-
lected by a hardware strapping option into the FER FAR
and PTR Configuration Registers The FCR PCR PMC
TUP and SID registers can only be accessed by software
An index and data register pair are used to read and write
the configuration registers Each Configuration Register is
pointed to the value loaded into the Index Register The
data to be written into the Configuration Register is trans-
ferred via the Data register A Configuration Register is read
in a similar way (i e by pointing to it via the Index Register
and then reading its contents via the Data Register)
Accessing the Configuration Registers in this way requires
only two system I O addresses Since I O address space is
shared by other devices the Index and Data Registers can
still be inadvertently accessed To reduce the chances of an
inadvertent access a simple procedure has been devel-
oped It is described in Section 2 2
2 2 SOFTWARE CONFlGURATlON
If the system requires access to the Configuration Registers
after reset the following procedure must be used to change
data in the registers
1 Determine the default location of the PC87332 Index
Register
Check the four possible locations (see Table 2-1) by
reading them twice The first byte is the ID byte 88h al-
though read-after-write always brings the value of the
written byte The second byte read is always 00h Com-
pare the data read with the ID byte and then 00h A
match occurs at the correct location Note that the ID
byte is only issued from the Index Register during the first
read after a reset Subsequent reads return the value
loaded into the Index Register Bits 4-6 are reserved and
always read 0
2 Load the Configuration Registers
A Disable CPU interrupts
B Write the index of the Configuration Register (00h –
0Eh) to the Index Register one time
C Write the correct data for the Configuration Register in
two consecutive write accesses to the Data Register
D Enable CPU interrupts
3 Load the Configuration Registers (read-modify-write)
A Disable CPU interrupts
B Write the index of the Configuration Register (00h –
0Eh) to the Index Register one time
C Read the configuration data in that register via the
Data Register
D Modify the configuration data
E Write the changed data for the Configuration Register
in two consecutive writes to the Data Register The
register updates on the second consecutive write
F Enable CPU interrupts
A single read access to the Index and Data Registers can
be done at any time without disabling CPU interrupts When
the Index Register is read the last value loaded into the
Index Register is returned When the Data Register is read
the Configuration Register data pointed to by the Index Reg-
ister is returned
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