PC87332VLJ Datasheet, PDF (13/98 Pages) National Semiconductor (TI) – PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac

1 0 Pin Description (Continued)
Symbol Pin I O
Function
IRQ5
98 I O Interrupt 5 Active high output that indicates a parallel port interrupt When enabled this bit follows the
ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is TRI-
STATE This pin is I O only when ECP is enabled and IRQ5 is configured For ECP operation refer to
the interrupt ECP Section 7 11 1
IRQ6
97
O Interrupt 6 Active high output to signal the completion of the execution phase for certain FDC
commands Also used to signal when a data transfer is ready during a Non-DMA operation When in
PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS 2 mode IRQ6 is
always enabled and bit D3 of the DOR is reserved
IRQ7
96 I O Interrupt 7 Active high output that indicates a parallel port interrupt When enabled this bit follows the
ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is
TRI-STATE This pin is I O only when ECP is enabled and IRQ7 is configured For ECP operation
refer to the interrupt ECP Section 7 11 1
MR
2
I Master Reset Active high input that resets the controller to the idle state and resets all disk interface
outputs to their inactive states The DOR DSR CCR Mode command Configure command and Lock
command parameters are cleared to their default values The Specify command parameters are not
affected The Configuration Registers are set to their selected default values
MFM
53 I O MFM (Modified Frequency Modulation) During a chip reset when lDENT is low this pin is sampled
to select the PS 2 mode (MFM high) or the Model 30 mode (MFM low) An internal pull-up or external
pull-down 10k resistor selects between the two PS 2 modes When the PC-AT mode is desired
(lDENT high) MFM should be left pulled high internally MFM reflects the current data encoding
format when RESET is inactive MFM e high Defaults to low after a chip reset (See IOCHRDY for
further information )
MTR0 1
Normal
Mode
46 43
O Motor Select 0 1 These are the motor enable lines for drives 0 and 1 and they are controlled by bits
D7–D4 of the Digital Output register They are active low outputs They are encoded with information
to control four FDDs when bit 4 of the Function Enable Register (FER) is set MTR0 exchanges logical
motor values with MTR1 when bit 4 of FCR is set (See DR0 1)
MTR1
PPM
Mode
84
O Motor Select 1 This pin provides an additional Motor Select 1 signal in PPM Mode when PNF e 0
This pin is the motor enable line for drive 1 when bit 4 of FCR is 0 It is the motor enable line for drive 0
when bit 4 of FCR is 1 This signal is active low (See BUSY and Table 7-5 for further information )
MSEN0 1
Normal
Mode
52 51
I Media Sense These pins are Media Sense input pins when bit 0 of FCR is 0 Each pin has a 10 kX
internal pull-up resistor When bit 0 of FCR is 1 these pins are Data Rate output pins and the pull-up
resistors are disabled (See DRATE0 1 for further information )
MSEN0 1
PPM
Mode
88 86
I Media Sense These pins provide additional Media Sense signals for PPM Mode and PNF e 0 (See
PD5 7 and Table 7-5 for further information )
PD
45
O Power-Down This pin is PD output when bit 4 of PMC is 1 It is DR1 when bit 4 of PMC is 0 PD is
active high whenever the FDC is in power-down state either via bit 6 of DSR (or bit 3 of FER or bit 0
of PTR) or via the mode command See DR1 for further information
PD0 – 7
94–91 I O Parallel Port Data These bidirectional pins transfer data to and from the peripheral data bus and the
89– 86
parallel port Data Register These pins have high current drive capability (See DC Electrical
Characteristics )
(See MSEN0 1 INDEX TRK0 WP RDATA DSKCHG and Table 7-5 for further information )
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