DS90CR483_04 Datasheet, PDF (7/22 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

AC Timing Diagrams
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FIGURE 1. “Worst Case” Test Pattern
Note 9: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
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FIGURE 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times
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FIGURE 4. DS90CR483 (Transmitter) Input Clock Transition Time
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