DS90CR483_04 Datasheet, PDF (10/22 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

AC Timing Diagrams (Continued)
FIGURE 10. DS90CR484 (Receiver) Phase Lock Loop Set Time
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FIGURE 11. DS90CR483 (Transmitter) Power Down Delay
FIGURE 12. DS90CR484 (Receiver) Power Down Delay
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