DS90CR483_04 Datasheet, PDF (19/22 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR484 Pin Description—Channel Link Receiver
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
Description
I
Positive LVDS differential data inputs.
I
Negative LVDS differential data inputs.
O
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are
forced to a Low state.
I
Positive LVDS differential clock input.
I
Negative LVDS differential clock input.
O
TTL level clock output. The rising edge acts as data strobe.
I
PLL range select. This pin should be tied to V_CC for auto-range. Tied to ground or
NC will force the PLL to low range only. Typical shift point is between 55 and 68
MHz for auto-range. (Notes 11, 12)
I
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample
feature this pin must be tied to V_CC. Tieing this pin to ground disables this feature.
(Note 11) Deskew is only supported in the DC Balance mode.
I
TTL level input. When asserted (low input) the receiver outputs are Low. (Note 11)
I
Power supply pins for TTL outputs and digital circuitry. Bypass not required on Pins
6 and 77.
I
Ground pins for TTL outputs and digital circuitry.
I
Power supply for PLL circuitry.
I
Ground pin for PLL circuitry.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
Note 13: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions
receiver inputs will be in a HIGH state. If the cable interconnect (media) are disconnected which results in floating/terminated inputs, the outputs will remain in the
last valid state.
Note 14: The DS90CR484 is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR483 and deserialize the LVDS
data according to the define bit mapping.
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