DS90CR483_04 Datasheet, PDF (18/22 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483 Pin Description—Channel Link Transmitter
Pin Name
TxIN
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
TxCLKM
PD
PLLSEL
PRE
DS_OPT
BAL
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
Description
I
TTL level input. (Note 11).
O
Positive LVDS differential data output.
O
Negative LVDS differential data output.
I
TTL level clock input. The rising edge acts as data strobe.
O
Positive LVDS differential clock output.
O
Negative LVDS differential clock output.
I
TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at
power down. (Note 11).
I
PLL range select. This pin should be tied to V_CC for auto-range. Tied to ground or
NC will force the PLL to low range only. Typical shift point is between 55 and 68
MHz for auto-range. (Notes 11, 12)
I
Pre-emphasis “level” select. Pre-emphasis is active when input is tied to V_CC
through external pull-up resistor. Resistor value determines Pre-emphasis level (See
Applications Information Section). For normal LVDS drive level (No Pre-emphasis)
leave this pin open (do not tie to ground).
I
Cable Deskew performed when TTL level input is low. No TxIN data is sampled
during Deskew. To perform Deskew function, input must be held low for a minimum
of 4 clock cycles. The Deskew operation is normally conducted after the TX and RX
PLLs have locked. It should also be conducted after a system reset, or a
reconfiguration event. It must be performed at least once when "DESKEW" is
enabled. (Note 11) Deskew is only supported in the DC Balance mode (BAL =
High).
I
TTL level input. This pin was previously labeled as V_CC, which enabled the DC
Balance function. But when tied low or left open, the DC Balance function is
disabled. Please refer to (Figures 15, 16) for LVDS data bit mapping respectively.
(Note 11), (Note 14)
I
Power supply pins for TTL inputs and digital circuitry. Bypass not required on Pins
20 and 21.
I
Ground pins for TTL inputs and digital circuitry.
I
Power supply pin for PLL circuitry.
I
Ground pins for PLL circuitry.
I
Power supply pin for LVDS outputs.
I
Ground pins for LVDS outputs.
No Connect. Make NO Connection to these pins - leave open.
Note 11: Inputs default to “low” when left open due to internal pull-down resistor.
Note 12: The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time. For 65-70 MHz applications, the DS90CR481/2
is recommended since its shift point is below its operation range. See Applications Information section.
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