DS90CF363 Datasheet, PDF (7/9 Pages) National Semiconductor (TI) – +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link─65 MHz

AC Timing Diagrams (Continued)
FIGURE 12. Transmitter LVDS Output Pulse Position Measurement
DS90CF363 Pin Description — FPD Link Transmitter
DS100032-20
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No.
I 21
O3
O3
I1
O1
O1
I1
I4
I4
I1
I2
I1
I
3
Description
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Applications Information
The DS90CF363 and DS90CF364 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CF563 and DS90CF564). To upgrade from a 5V to a
3.3V system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V_CC, LVDS V_CC and PLL V_CC of both the transmitter
and receiver devices. This change may enable the re-
moval of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2. The DS90CF363 transmitter input and control inputs ac-
cept 3.3V TTL/CMOS levels. They are not 5V tolerant.
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