DS90CF363 Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link─65 MHz

January 2000
DS90CF363
+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)
Link— 65 MHz
General Description
The DS90CF363 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. At a transmit clock frequency of 65 MHz, 18
bits of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 170 Mbytes/sec.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption < 250 mW (typ)
n Power-down mode (< 0.5 mW total)
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 170 Megabytes/sec bandwidth
n Up to 1.3 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Falling edge data strobe Transmitter
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating > 7 kV
n Operating Temperature: −40˚C to +85˚C
Block Diagram
DS90CF363
Order Number DS90CF363MTD
See NS Package Number MTD48
DS100032-1
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© 2000 National Semiconductor Corporation DS100032
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