DS90C363 Datasheet, PDF (7/16 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link─65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link─65 MHz

AC Timing Diagrams (Continued)
FIGURE 2. “16 Grayscale” Test Pattern (Notes 6, 7, 8, 9)
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Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 9: Recommended pin to signal mapping. Customer may choose to define differently.
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FIGURE 3. DS90C363 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 4. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times
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FIGURE 5. DS90C363 (Transmitter) Input Clock Transition Time
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