DS90C363 Datasheet, PDF (5/16 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link─65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link─65 MHz

Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 3 )
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3 )
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 5 )
5
ns
TCCS
TxOUT Channel-to-Channel Skew (Figure 6 )
250
ps
TPPos0
Transmitter Output Pulse Position for Bit 0
(Figure 17 )
f = 65 MHz
−0.4
0
0.3
ns
TPPos1 Transmitter Output Pulse Position for Bit 1
1.8
2.2
2.5
ns
TPPos2 Transmitter Output Pulse Position for Bit 2
4.0
4.4
4.7
ns
TPPos3 Transmitter Output Pulse Position for Bit 3
6.2
6.6
6.9
ns
TPPos4 Transmitter Output Pulse Position for Bit 4
8.4
8.8
9.1
ns
TPPos5 Transmitter Output Pulse Position for Bit 5
10.6
11.0
11.3
ns
TPPos6 Transmitter Output Pulse Position for Bit 6
12.8
13.2
13.5
ns
TCIP
TxCLK IN Period (Figure 7)
15
T
50
ns
TCIH
TxCLK IN High Time (Figure 7)
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 7)
0.35T
0.5T
0.65T
ns
TSTC
TxIN Setup to TxCLK IN (Figure 7 )
f = 65 MHz
2.5
ns
THTC
TxIN Hold to TxCLK IN (Figure 7 )
0
ns
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay 25˚C, V_CC = 3.3V (Figure 9 )
Transmitter Phase Lock Loop Set (Figure 11 )
3.0
3.7
5.5
ns
10
ms
TPDD
Transmitter Power Down Delay (Figure 15 )
100
ns
5
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