DS90C363 Datasheet, PDF (13/16 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link─65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link─65 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
Note 11: ISI is dependent on interconnect length; may be zero.
FIGURE 19. Receiver LVDS Input Skew Margin
DS90C363 Pin Description — FPD Link Transmitter
DS012886-11
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
RTxCLK OUT+
TxCLK OUT−
PWR DWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No.
I 21
O3
O3
I
1
I
1
O1
O1
I
1
I
3
I
4
I
1
I
2
I
1
I
3
Description
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
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