DS90C363 Datasheet, PDF (6/16 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link─65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link─65 MHz

Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
Receiver Input Strobe Position for Bit 0 (Figure 18 ) f = 65 MHz
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 19 )
f = 65 MHz
RxCLK OUT Period (Figure 8)
RxCLK OUT High Time (Figure 8 )
f = 65 MHz
RxCLK OUT Low Time (Figure 8)
f = 65 MHz
RxOUT Setup to RxCLK OUT (Figure 8 )
f = 65 MHz
RxOUT Hold to RxCLK OUT (Figure 8 )
f = 65 MHz
RxCLK IN to RxCLK OUT Delay 25˚C, V_CC = 3.3V (Figure 10 )
Receiver Phase Lock Loop Set (Figure 12 )
Receiver Power Down Delay (Figure 16 )
Min
Typ
Max
Units
2.2
5.0
ns
2.2
5.0
ns
0.7
1.1
1.4
ns
2.9
3.3
3.6
ns
5.1
5.5
5.8
ns
7.3
7.7
8.0
ns
9.5
9.9
10.2
ns
11.7
12.1
12.4
ns
13.9
14.3
14.6
ns
400
ps
15
T
50
ns
7.3
8.6
ns
3.45
4.9
ns
2.5
6.9
ns
2.5
5.7
ns
5.0
7.1
9.0
ns
10
ms
1
µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-
ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012886-2
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