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COP8ACC7 Datasheet, PDF (7/40 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D | |||
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DC Electrical Characteristics (Continued)
â40ËC ⤠TA ⤠+85ËC unless otherwise specified
Parameter
Input Capacitance
(Note 14)
Load Capacitance on D2
(Note 14)
Conditions
Min
Typ
Max
Units
7
pF
1000
pF
AC Electrical Characteristics
â40ËC ⤠TA ⤠+85ËC unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (Note 16)
Crystal, Resonator
R/C Oscillator
Inputs
2.7V ⤠VCC< 4V
2.5
4V ⤠VCC ⤠5.5V
1.0
2.7V ⤠VCC < 4V
7.5
4V ⤠VCC < 5.5V
3.0
DC
µs
DC
µs
DC
µs
DC
µs
tSETUP
4V ⤠VCC ⤠5.5V
200
2.7V ⤠VCC < 4V
500
tHOLD
4V ⤠VCC ⤠5.5V
60
2.7V ⤠VCC< 4V
150
Output Propagation Delay (Note 14)
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
4V ⤠VCC ⤠5.5V
2.7V ⤠VCC < 4V
All Others
4V ⤠VCC ⤠5.5V
2.7V ⤠VCC< 4V
MICROWIRE Setup Time (tUWS) (Note 14)
VCC ⥠4V
20
MICROWIRE Hold Time (tUWH) (Note 14)
VCC ⥠4V
56
MICROWIRE Output Propagation Delay (tUPD)
VCC ⥠4V
Input Pulse Width (Note 15)
ns
ns
ns
ns
0.7
µs
1.75
µs
1
µs
2.5
µs
ns
ns
220
ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1
tC
1
tC
1
tC
1
tC
1
µs
Note 10: Maximum rate of voltage change must be < 0.5 V/ms.
Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 12: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing or
sinking current; with L, C, and G0âG5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC;
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal
clock mode.
Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750⦠(typical).
These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This
warning excludes ESD transients.
Note 14: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 15: Parameter characterized but not tested.
Note 16: tC = Instruction Cycle Time.
7
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