COP8ACC7 Datasheet, PDF (11/40 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D

Pin Descriptions (Continued)
Configuration Data
Register
Register
Port Set-Up
0
0
Hi-Z Input (TRI-STATE Output)
0
1
Input with Weak Pull-Up
1
0
Push-Pull Zero Output
1
1
Push-Pull One Output
Please note:
The lower 4 L-bits read all ones (L0:L3). This is independant
from the states of the associated bits in the L-port Data- and
Configuration register. The lower 4 bits in the L-port Data-
and Configuration register can be used as general purpose
status indicators (flags).
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option se-
lected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-
vidually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose in-
put (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and G7
data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config Reg.
Data Reg.
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated
output.
Port I is an eight-bit Hi-Z input port.
Port I0–I7 are used for the analog function block.
The Port I has the following alternate features:
I7 C_OUT (Comparator Output)
I6 Analog CH6 (Comparator Positive Input 6)
I5 Analog CH5 (Comparator Positive Input 5)
I4 Analog CH4 (Comparator Positive Input 4)
I3 Analog CH3 (Comparator Positive Input 3/Comparator
Output)
I2 Analog CH2 (Comparator Positive Input 2)
I1 I_SRC (Comparator Negative Input/Current Source Out)
I0 Analog CH1 (Comparator Positive Input 1)
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex-
cept D2) together in order to get a higher drive.
Functional Description
The architecture of the device is a modified Harvard archi-
tecture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on the Harvard architecture, per-
mits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t_C) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC^® is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 16,384 bytes of OTP
EPROM. These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS in-
struction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature and can only be asserted after
the memory array has been programmed and verified. A se-
cured part will read all 00(hex) by a programmer. The part
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