COP8ACC7 Datasheet, PDF (16/40 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D

Timers (Continued)
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
T1C3 Timer mode control
T1C2 Timer mode control
T1C1 Timer mode control
T1C0
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
T1PNDA Timer Interrupt Pending Flag
T1ENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
T1PNDB Timer Interrupt Pending Flag
T1ENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:
Mode
1
2
3
T1C3
1
1
0
0
0
1
0
1
T1C2
0
0
0
0
1
1
1
1
T1C1
1
0
0
1
0
0
1
1
Description
PWM: T1A Toggle
PWM: No T1A
Toggle
External Event
Counter
External Event
Counter
Captures:
T1A Pos. Edge
T1B Pos. Edge
Captures:
T1A Pos. Edge
T1B Neg. Edge
Captures:
T1A Neg. Edge
T1B Neg. Edge
Captures:
T1A Neg. Edge
T1B Neg. Edge
Interrupt A
Source
Autoreload RA
Autoreload RA
Interrupt B
Source
Autoreload RB
Autoreload RB
Timer
Underflow
Timer
Underflow
Pos. T1A Edge
or Timer
Underflow
Pos. T1A
Edge or Timer
Underflow
Neg. T1A
Edge or Timer
Underflow
Neg. T1A
Edge or Timer
Underflow
Pos. T1B Edge
Pos. T1B Edge
Pos. T1B Edge
Neg. T1B
Edge
Neg. T1B
Edge
Neg. T1B
Edge
Timer
Counts On
t_C
t_C
Pos. T1A
Edge
Pos. T1A
Edge
t_C
t_C
t_C
t_C
HIGH SPEED CAPTURE TIMER
The device provides a 16-bit high-speed capture timer. The
timer consists of a 16-bit up-counter that is clocked with the
device clock input frequency (CKI) and an 8-bit control regis-
ter. The 16-bit counter is mapped as two read/write 8-bit reg-
isters. This timer is specifically designed to be used in con-
junction with the Analog Function Block (comparator, analog
multiplexer, constant current source) to implement a
low-cost, high-resolution, single-slope A/D.
The timer is automatically stopped in the event of a capture
to allow the software to read the timer value. Coming out of
reset the counter is disabled (stopped) and reads all “0”.
Setting the Capture Timer Run bit CAPRUN bit in the Cap-
ture Control Register (CAPCNTL) will start the counter. The
counter will count up until a capture event (negative edge) is
received. Upon a capture the counter will be stopped, the
Capture Pending bit (CAPPND) is set, and the CAPRUN bit
is automatically reset. If capture interrupts are enabled
(CAPIEN=1), the capture event will generate an interrupt.
Setting the CAPRUN bit again by software will start a new
counting cycle. If the Capture Mode bit is reset (CAP-
MOD=0) the capture timer will be automatically initialized to
all “0” with each setting of the CAPRUN bit. If CAPMOD=1
the timer will not be cleared when setting the CAPRUN bit,
thus allowing the user’s software to pre-load the timer regis-
ters with any desired value. This mode can be used in con-
junction with the timer’s overflow to implement for example a
programmable delay counter.
“CAPTURE MODE” is only active when the CAPRUN bit is
set, i.e. any capture events received while the timer is
stopped (CAPRUN=0) will be ignored and will not cause the
CAPPND bit to be set. The capture counter can also be
stopped (frozen) by the user’s software resetting the CA-
PRUN bit.
If the user program tries to set the CAPRUN bit at the same
time that the hardware gets a capture event and tries to reset
the CAPRUN bit, the hardware will have precedence.
Should the counter overflow before a capture condition oc-
curs, the Capture Overflow bit (CAPOVL) bit in the
CAPCNTL register will be set. If Capture interrupts are en-
abled (CAPIEN=1) an overflow will generate an interrupt.
The user software should reset this bit before the next over-
flow occurs, otherwise subsequent overflow conditions can-
not be detected.
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