COP8ACC7 Datasheet, PDF (5/40 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D

DC Electrical Characteristics (Continued)
0˚C ≤ T_A ≤ +70˚C unless otherwise specified
Parameter
Input Capacitance
(Note 6)
Load Capacitance on D2
(Note 6)
Conditions
Min
Typ
Max
Units
7
pF
1000
pF
AC Electrical Characteristics
0˚C ≤ T_A ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (Note 8)
Crystal, Resonator
R/C Oscillator
Inputs
2.7V ≤ V_CC ≤ 4V
2.5
4V ≤ V_CC ≤ 5.5V
1.0
2.7V ≤ V_CC ≤ 4V
7.5
4V ≤ V_CC ≤ 5.5V
3.0
DC
µs
DC
µs
DC
µs
DC
µs
t_SETUP
4V ≤ V_CC ≤ 5.5V
200
2.7V ≤ V_CC ≤ 4V
500
t_HOLD
4V ≤ V_CC ≤ 5.5V
60
2.7V ≤ V_CC ≤ 4V
150
Output Propagation Delay (Note 6)
R_L = 2.2k, C_L = 100 pF
t_PD1, t_PD0
SO, SK
4V ≤ V_CC ≤ 5.5V
2.7V ≤ V_CC ≤ 4V
All Others
4V ≤ V_CC ≤ 5.5V
2.7V ≤ V_CC ≤ 4V
MICROWIRE™ Setup Time (t_UWS) (Note 6)
V_CC ≥ 4V
20
MICROWIRE Hold Time (t_UWH) (Note 6)
V_CC ≥ 4V
56
MICROWIRE Output Propagation Delay (t_UPD)
V_CC ≥ 4V
Input Pulse Width (Note 7)
ns
ns
ns
ns
0.7
µs
1.75
µs
1
µs
2.5
µs
ns
ns
220
ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1
t_C
1
t_C
1
t_C
1
t_C
1
µs
Note 2: Maximum rate of voltage change must be < 0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I_DD HALT is done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V_CC;
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal
clock mode.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > V_CC and the pins will have sink current to V_CC when
biased at voltages > V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 7: Parameter characterized but not tested.
Note 8: t_C = Instruction Cycle Time.
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