NSBMC096-16 Datasheet, PDF (6/18 Pages) National Semiconductor (TI) – NSBMC096-16/-25/-33 Burst Memory Controller

Functional Description
PRODUCT OVERVIEW
The NSBMC960 couples the i960 CA CF interface to
DRAM access protocols generates bus buffer and data
multiplexor controls and incorporates system and bus moni-
tor timing resources These functional elements are shown
in Figure 1 A maximum of 8 controllers may be included in a
system each managing up to 4 banks of memory
The NSBMC960 directly drives an array of fast page mode
DRAMs This array may be organized as 1 or 2 leaves of
32 bits each Standard memory sizes from 256 kbit to
64 Mbit are supported and 8- 16- and 32-bit access are
allowed If interleaved mode is selected burst access is
zero-wait-state if memory is non-interleaved 1-wait-state
burst access results
The NSBMC960 allows for flexibility in the control of data
buffers to the memory array Propagation delay is minimized
by providing these controls directly and design flexibility
maximized by allowing the control strategy to be program-
mable Buffers as diverse as 74FCT245 74FCT543
74FCT646 74FCT853 and 74FCT861 may be used without
additional glue logic
FIGURE 1 Functional Block Diagram
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CONFIGURATION AND CONTROL
The NSBMC960 contains 64 bits of configuration data that
controls it’s operational mode The configuration is pro-
grammed by sending data on the address bus Figure 2
shows the format of a configuration access The byte select
field determines which byte of the 64-bit field will be updat-
ed by the contents of the byte data field Bits 1 0 are re-
served and must be ‘‘0’’ The base address is fixed at
0xff0f0000 while the BMC select field must match the value
programmed at the ID 2 0 pins In order to protect against
accidental programming the configuration registers can
only be modified when the processor is in supervisor mode
FIGURE 2 Address Bus Fields Used to Access Configuration Data
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