NSBMC096-16 Datasheet, PDF (15/18 Pages) National Semiconductor (TI) – NSBMC096-16/-25/-33 Burst Memory Controller

AC Timing Parameters (Unless otherwise stated V_CC e 5 0V g5% 0 C ^k T_A ^k 70 C )
Symbol
Description
16 MHz
Min Max
25 MHz
Min Max
33 MHz
Min Max
Units
1 t_ADSU Address Strobe Setup Time
14
12
9
ns
2 t_ADH Address Strobe Hold Time
3
3
3
ns
3 t_SU
Synchronous Input Setup
14
12
9
ns
4 t_H
Synchronous Input Hold
3
3
3
ns
5 t_BLSU BLAST Input Setup
14
12
9
ns
6 t_BLH
BLAST Input Hold
3
3
3
ns
7 t_RZH READY 3-state to Valid Delay Relative to PCLK
29
24
19
ns
8 t_RHL
READY Synchronous Assertion Delay
26
21
17
ns
9 t_RLH
READY Synchronous De-assertion Delay
25
20
16
ns
10 t_RHZ READY Valid to 3-state Delay Relative to PCLK
27
22
17
ns
11 t_ARA Address Input to Row Address Output Delay (Note 1)
23
19
15
ns
12 t_RAH
PCLK or PCLK to Row Address Hold
40
33
26
ns
13 t_CAV
PCLK or PCLK to Column Address Valid (Note 1)
38
31
25
ns
14 t_CAH PCLK to Column Address Hold
4
4
4
ns
15 t_DRAH DRAM Row Address Hold (Note 2)
t_M-4
t_M-4
t_M-3
ns
16 t_RSHL PCLK to RAS Asserted Delay (Note 1)
29
24
19
ns
17 t_RSLH PCLK to RAS De-asserted Delay (Note 1)
26
21
17
ns
18 t_CHL
PCLK to CAS Asserted Delay (Note 1)
23
19
15
ns
19 t_CLH
PCLK to CAS De-asserted Delay (Note 1)
20
16
13
ns
20 t_BHL
PCLK to Buffer Control Asserted Delay (Note 1)
26
21
17
ns
21 t_BLH
PCLK to Buffer Control De-asserted Delay (Note 1)
4
23
4
19
4
15
ns
22 t_BSV
PCLK to Bank Select Valid Time (Note 1)
26
21
17
ns
23 t_BSH PCLK to Bank Select Hold Time (Note 1)
4
4
4
ns
24 t_WEHL PCLK to Write Enable Asserted Delay (Note 1)
31
25
20
ns
25 t_WELH PCLK to Write Enable De-asserted Delay (Note 1)
ns
26 t_BCAH PCLK to Column Address Hold Time (Burst) (Note 1)
5
5
4
ns
27 t_BCAV PCLK to Column Address Valid Delay (Burst) (Note 1)
29
23
19
ns
28 t_LEHL
PCLK to Latch Enable Assertion
23
19
15
ns
29 t_LELH PCLK to Latch Enable De-assertion
20
16
13
ns
30 t_RFA
PCLK to Row Address Valid (Refresh)
38
31
25
ns
31 t_RFH PCLK to Row Address Hold (Refresh)
5
5
4
ns
32 t_RFHL REFRESH Synchronous Assertion Delay
20
16
13
ns
33 t_RFLH REFRESH Synchronous De-assertion Delay
20
16
13
ns
Signal output delays are measured relative to PCLK (except as indicated) using a 50 pF load
Note 1 Derate the given delays by 0 006 ns per pF of load in excess of 50 pF
Note 2 t_M e PCLK High duration when configuration bit 18 e 0 t_M e PCLK cycle time e 1 _{(PCLK frequency)} for configuration bit 18 e 1 Timing for Rev AB
silicon
15