NSBMC096-16 Datasheet, PDF (13/18 Pages) National Semiconductor (TI) – NSBMC096-16/-25/-33 Burst Memory Controller

Timing Parameters (Continued)
FIGURE 8 Burst Access w t PCache Hit
TL V 11805 – 11
Figures 8 and 9 show the sequence of events that can oc-
cur when PCache is enabled The sequence in Figure 8
shows two back-to-back bursts in the same page This type
of sequence yields the highest data transfer rate achievable
with DRAM Figure 9 shows the worst case scenario This
example shows two back-to-back simple access to different
rows with PCache is enabled
FIGURE 9 Simple Access w t PCache Miss
13
TL V 11805 – 12