NSBMC096-16 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – NSBMC096-16/-25/-33 Burst Memory Controller

Pin Descriptions
TABLE I
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
1
A14
2
A15
3
A16
4
V_CC
5
A17
6
A19
44
LEB
45
TXA
46
TXB
47
V_CC
48
V_SS
53
AA0
91
V_CC
92
V_SS
93
AB4
94
AB5
95
AB6
96
AB7
7
A20
8
A18
9
A21
10
A24
11
A22
12
A23
54
AA1
55
AA2
56
AA3
57
V_CC
58
V_SS
59
AA4
97
V_CC
98
V_SS
99
AB8
100
AB9
101
AB10
102
AB11
13
A26
14
A25
15
A27
19
A31
20
A28
21
A29
60
AA5
61
AA6
62
AA7
63
V_CC
64
V_SS
65
AA8
103
V_CC
104
V_SS
105
CASB0
106
CASB1
107
CASB2
108
CASB3
22
A30
23
DC
24
SUP
25
PCLK
26
INT
27
BERR
66
AA9
67
AA10
68
AA11
69
V_CC
70
V_SS
71
CASA0
109
V_CC
110
V_SS
111
RASB0
112
RASB1
113
RASB2
114
RASB3
28
WR
29
BE0
30
DEN
31
BLAST
32
BE1
33
V_SS
34
ADS
35
BE2
36
BE3
37
BTERM
38
READY
39
ID0
40
ID1
41
ID2
42
REFRESH
43
LEA
72
CASA1
73
CASA2
74
CASA3
75
V_CC
76
V_SS
77
RASA0
78
RASA1
79
RASA2
80
RASA3
81
V_CC
82
MWEA
86
V_SS
87
AB0
88
AB1
89
AB2
90
AB3
115
V_CC
118
MWEB
119
V_SS
120
RESET
121
A2
122
A3
123
A4
124
A5
125
A6
126
A7
127
A8
128
A9
129
A10
130
A11
131
A12
132
A13
Note In order for the switching characteristics of this device to be guaranteed it is necessary to connect all of the power pins (V_CC V_SS) to the appropriate power
levels The use of low impedance wiring to the power pins is required In systems using the i960 CA with its attendant high switching rates multi-layer printed circuit
boards with buried power and ground planes are required
3