LP2995 Datasheet, PDF (6/13 Pages) National Semiconductor (TI) – DDR Termination Regulator

Block Diagram
Description
The LP2995 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
LP2995 is capable of sinking and sourcing current at the
output V_TT, regulating the voltage to equal VDDQ / 2. A
buffered reference voltage that also tracks VDDQ / 2 is
generated on the V_REF pin for providing a global reference to
the DDR-SDRAM and Northbridge Chipset. V_TT is designed
to track the V_REF voltage with a tight tolerance over the
entire current range while preventing shoot through on the
output stage.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR RAM. The most common
form of termination is Class II single parallel termination. This
involves using one Rs series resistor from the chipset to the
memory and one Rt termination resistor. This implementa-
tion can be seen below in Figure 1.
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Typical values for R_S and R_T are 25 Ohms although these
can be changed to scale the current requirements from the
LP2995. For determination of the current requirements of
DDR-SDRAM termination please refer to the accompanying
application notes.
FIGURE 1.
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