LP2995 Datasheet, PDF (3/13 Pages) National Semiconductor (TI) – DDR Termination Regulator

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, AVIN, VDDQ to GND
Storage Temp. Range
Junction Temperature
SO-8 Thermal Resistance (θ_JA)
LLP-16 Thermal Resistance (θ_JA)
−0.3V to +6V
−65˚C to +150˚C
150˚C
151˚C/W
51˚C/W
Lead Temperature (Soldering, 10 sec)
ESD Rating (Note 7)
Operating Range
Junction Temp. Range (Note 5)
AVIN to GND
PVIN to GND
260˚C
1kV
0˚C to +125˚C
2.2V to 5.5V
2.2V to AVIN
Electrical Characteristics Specifications with standard typeface are for T_J = 25˚C and limits in boldface
type apply over the full Operating Temperature Range (T_J = 0˚C to +125˚C). Unless otherwise specified,
AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6).
Symbol
V_REF
VOS_VTT
∆V_TT/V_TT
Z_VREF
Z_VDDQ
I_q
Parameter
V_REF Voltage
V_TT Output Voltage Offset
Load Regulation
(Note 3)
V_REF Output Impedance
VDDQ Input Impedance
Quiescent Current
Conditions
I_{REF_OUT} = 0mA
I_OUT = 0A
(Note 2)
I_OUT = 0 to 1.5A
I_OUT = 0 to −1.5A
I_REF = −5µA to +5µA
I_OUT = 0A
(Note 4)
Min
Typ
Max
Units
1.21
1.235
1.26
V
−15
0
15
mV
−20
20
0.5
%
−0.5
5
kΩ
100
kΩ
250
400
µA
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: V_TT offset is the voltage measurement defined as V_TT subtracted from V_REF.
Note 3: Load regulation is tested by using a 10ms current pulse and measuring V_TT.
Note 4: Quiescent current defined as the current flow into AVIN.
Note 5: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θ_JA = 151˚ C/W
junction to ambient with no heat sink. The device in the LLP-16 must be derated at θ_JA = 51˚ C/W junction to ambient.
Note 6: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 7: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
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