LMH0030_0608 Datasheet, PDF (6/29 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver

DC Electrical Characteristics (Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
Reference
Min Typ
Max
Units
I_DD (3.3V) Power Supply Current,
3.3V Supply, Total
V_CLK = 74.25 MHz, NTSC
color Bar Pattern, Test
Circuit, Test Loads Shall
Apply
V_DDIO, V_DDSD
66
90
mA
I_DD (2.5V) Power Supply Current,
2.5V Supply, Total
V_CLK = 27 MHz, NTSC
color Bar Pattern, Test
Circuit, Test Loads Shall
Apply
V_DDD, V_DDZ,
V_DDPLL
66
85
mA
I_DD (2.5V) Power Supply Current,
2.5V Supply, Total
V_CLK = 74.25 MHz, NTSC
color Bar Pattern, Test
Circuit, Test Loads Shall
Apply
V_DDD, V_DDZ,
V_DDPLL
85
110
mA
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min Typ
f_VCLK
Parallel Video Clock
Frequency
V_CLK
27
DC_V
Video Clock Duty
Cycle
V_CLK
45
50
f_ACLK
Ancillary Clock
Frequency
A_CLK
DC_A
Ancillary Clock Duty
Cycle
A_CLK
45
50
t_r, t_f
BR_SDO
t_r, t_f
t_r, t_f
Input Clock and Data
Rise Time, Fall Time
Serial Data Rate
Rise Time, Fall Time
Rise Time, Fall Time
Output Overshoot
10%–90%
(Notes 5, 6)
20%–80%, (Note 6)
20%–80%, (Note 5)
(Note 4)
V_CLK, A_CLK, DV_N, _1.0
1.5
AD_N
SDO, SDO
270
SDO, SDO
SDO, SDO
500
SDO, SDO
5
t_j
Serial Output Jitter,
270 M_bps, (Notes 5, 9, 10, 11)
SDO, SDO
270
Intrinsic
t_j
Serial Output Jitter,
1,485 M_bps, (Notes 6, 9, 10, 11) SDO, SDO
85
Intrinsic
t_LOCK
Lock Time
(Notes 5, 7) (SD Rates)
15
t_LOCK
Lock Time
(Notes 6, 7) (HD Rates)
15
t_S
Setup Time, Video
Timing Diagram, (Note 4)
DV_N to V_CLK
1.5
Data
t_H
Hold Time, Video Data Timing Diagram, (Note 4)
V_CLK to DV_N
1.5
t_S
Setup Time, Anc. Data Timing Diagram, (Note 4)
AD_N to A_CLK
1.5
Port
t_H
Hold Time, Anc. Data Timing Diagram, (Note 4)
A_CLK to AD_N
1.5
Port
Max
74.25
55
V_CLK
55
3.0
1,485
270
350
125
2.0
2.0
2.0
2.0
Units
MHz
%
MHz
%
ns
M_bps
ps
ps
%
ps_P-P
ps_P-P
ms
ms
ns
ns
ns
ns
Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”
specifies acceptable device operating conditions.
Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to V_SS = 0V.
Note 3: Typical values are stated for V_DDIO = V_DDSD = +3.3V, V_DDD = V_DDPLL = +2.5V and T_A = +25˚C.
Note 4: Specification is guaranteed by design.
Note 5: R_L = 75Ω, AC-coupled @ 270 M_bps, R_REFLVL = R_REFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit.
Note 6: R_L = 75Ω, AC-coupled @ 1,485 M_bps, R_REFLVL = R_REFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit.
Note 7: Measured from rising-edge of first DV_CLK cycle until Lock Detect output goes high (true). Lock time includes format detection time plus PLL lock time.
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