LMH0030_0608 Datasheet, PDF (13/29 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver

Device Operation (Continued)
supplied power via external low-pass filters, if desired. PLL
acquisition time is less than 200µs @ 1485 Mbps. The VCO
halts when the V_CLK signal is not present or is inactive.
A LOCK DETECT indicator function is available as a bit in
the VIDEO INFO 0 control registers. LOCK DETECT is a
logic-1 when the PLL is locked and a valid format has been
detected. It can be assigned as an output on the multifunc-
tion I/O port. By default LOCK DETECT is assigned as I/O
Port bit 4 after power-on or reset . This function also includes
logic to check the stability of the device after the digital logic
reset is released following PLL lock. If the system is not fully
stable, the logic is automatically reset. LOCK DETECT also
combines the function of indicating that the LMH0030 has
detected the video format being received. This format detect
function involves determination of the major raster param-
eters such as line length, number of video lines in a frame,
and so forth. This is done so that information like line num-
bering can be correctly inserted. The PLL itself will have
locked in 200 microseconds (HD rates) or less. However,
resolution of all raster parameters may take the majority of a
frame.
SERIAL DATA OUTPUT DRIVER
The serial data outputs provide low-skew complimentary or
differential signals. The output buffer is a current-mode de-
sign and is intended to drive AC-coupled and terminated,
75Ω coaxial cables. The driver automatically adjusts its out-
put slew rate depending upon the data rate being processed.
Output levels are 800 mV_P-P ±10% into 75Ω AC-coupled
loads. The 75Ω resistors connected to the SDO outputs
function both as drain-load and back-matching resistors.
Series back-matching resistors are not used with this output
type.
The serial output level is controlled by the value of R_REFLVL
and R_REFPRE connected to pin 53 and pin 52, respectively.
The R_REFLVL resistor sets the peak-to-peak level of the
output signal to the required SMPTE nominal level. The
R_REFPRE resistor sets the value of a pre-emphasis current
which is active during the transition times of the HD-rate
output signal. The value of R_REFLVL is normally 4.75 KΩ,
±1%. The value of R_REFPRE is normally 4.75 KΩ, ±1%. The
voltage present at these pins is approximately +1.3Vdc. The
transition times of this output buffer design automatically
adjust and are different for the HD and SD data rate condi-
tions. The output buffer is quiescent when the device is in an
out-of-lock condition. The output will become active after the
PLL is locked and a valid format has been detected. Sepa-
rate power feeds are provided for the serial output driver:
V_SSSD, pins 54, 55, and 59; V_DDSD, pin 51; and V_DDLS, pin
57.
CAUTION: This output buffer is not designed or specified for
driving 50Ω or other impedance loads.
POWER SUPPLIES, POWER-ON-RESET AND RESET
INPUT
The LMH0030 requires two power supplies, 2.5V for the core
logic functions and 3.3V for the I/O functions. The supplies
must be applied to the device in proper sequence. The 3.3V
supply must be applied prior to or coincident with the 2.5V
supply. Application of the 2.5V supply must not precede the
3.3V supply. It is recommended that the 3.3V supply be
configured or designed so as to control application of the
2.5V supply in order to satisfy this sequencing requirement.
The LMH0030 has an automatic, power-on-reset circuit.
Reset initializes the device and clears TRS detection cir-
cuitry, all latches, registers, counters and polynomial genera-
tors, sets the EDH/CRC characters to 00h and disables the
serial output. Table 1 lists the initial conditions of the con-
figuration and control registers. An active-HIGH-true, manual
reset input is available at pin 64. The reset input has an
internal pull-down device and may be considered inactive
when unconnected.
Important: When power is first applied to the device or
following a reset, the Ancillary and Control Data Port must
be initialized to receive data. This is done by toggling ACLK
three times.
TEST PATTERN GENERATOR (TPG) AND BUILT-IN
SELF-TEST (BIST)
The LMH0030 includes a built-in test pattern generator
(TPG). Four test pattern types are available for all data rates,
all HD and SD formats, NTSC and PAL standards, and 4x3
and 16x9 raster sizes. The test patterns are: flat-field black,
PLL pathological, equalizer (EQ) pathological and a 75%,
8-color vertical bar pattern. The pathologicals follow the
recommendations of SMPTE RP 178-1996 regarding the
test data used. The color bar pattern has optional bandwidth
limiting coding in the chroma and luma data transitions be-
tween bars. The VPG FILTER ENABLE bit in the VIDEO
INFO 0 control register enables the color bar filter function.
The default condition of VPG FILTER ENABLE is OFF.
The TPG also functions as a built-in self-test (BIST) which
can verify device functionality. The BIST function performs a
comprehensive go/no-go test of the device. The test may be
run using any of the HD color bar test patterns or one of two
SD test patterns, either a 270 Mbps NTSC full-field color bar
or a PAL PLL pathological, as the test data pattern. Data is
supplied internally in the input data register, processed
through the device and tested for errors using either the EDH
system for SD or the CRC system for HD. A go/no-go indi-
cation is logged in the Pass/Fail bit of the TEST 0 control
register set. This bit may be assigned as an output on the
multifunction I/O port.
TPG and BIST operation is initiated by loading the code for
the desired test pattern into the Test Pattern Select [5:0]
bits of the TEST 0 register. Table 5 gives the available test
patterns and codes. (Recall also the requirement to initialize
the ancillary data port control logic by clocking ACLK at least
three (3) complete cycles before attempting to load the first
register address). In the default power-on state, TPG Enable
appears as bit 7 on the multi-function I/O port. The TPG is
run by applying the appropriate frequency at the VCLK input
for the format and rate selected and then setting the TPG
Enable input on the multi-function I/O port, or by setting the
TPG Enable bit in the TEST 0 register.
Important: If the TPG Enable input of the I/O port is in its
default mapping and is not being used to enable the TPG
mode, attempting to enable TPG operation by setting bit 6 of
the TEST 0 register will not cause the TPG to operate. This
is because the low logic level at the I/O port input pulldown
overrides the high level being written to the register. The
result is the TPG does not run.
The Pass/Fail bit in the TEST 0 control register indicates the
test status. If no errors have been detected, this bit will be
set to logic-1 approximately 2 field intervals after TPG En-
able is set. If errors have been detected in the internal
circuitry of the LMH0030, Pass/Fail will remain reset to a
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