LMH0030_0608 Datasheet, PDF (21/29 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver

Device Operation (Continued)
the insertion of transition codes in the chroma and luma data
of color bar test patterns where these patterns change from
one bar to the next. This filter reduces the magnitude of
out-of-band frequency products which can be produced by
abrupt transitions in the chroma and luma data when fed to
D-to-A converters and picture monitors. The default condi-
tion of this bit is reset (off).
A method by which the occurrence of pathological data
patterns can be prevented has been proposed for SD for-
mats. The LMH0030 implements this process for SD for-
mats. The Dither Enable and Vertical Dither Enable bits
control operation of pseudo-random dithering applied to the
two LSBs of the video data. Dithering is applied to active
video data when the Dither Enable bit is set. When the
Vertical Dither Enable bit is set, dithering is applied to that
portion of the video line corresponding to active video for
lines in the vertical blanking interval.
I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS
(Addresses 0Fh through 16h)
The Multi-function I/O Bus Pin Configuration registers are
used to map the bits of the multi-function I/O port to selected
bits of the Configuration and Control Registers. Table 6
details the available Configuration and Control register bit
functions that may be mapped to the port and their corre-
sponding mapping addresses. Pin # SEL[5] in each register
indicates whether the port pin is input or output. The port pin
will be an input when this bit is set and an output when reset.
Input-only functions may not be configured as outputs and
vice versa. The remaining lower-order five address bits dis-
tinguish the particular function.
Example: Program, via the AD port, I/O port bit 0 as output
for the CRC Luma Error bit in the control registers.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-low.
3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG
register address.
4. Toggle ACLK.
5. Present 310h to AD[9:0] as the register data, the bit
address of the CRC Luma Error bit in the control regis-
ters.
6. Toggle ACLK.
TEST MODE 0 REGISTER (Address 55h)
The four bits of this register are intended for use as test
mode functions. They are not normal operating modes. The
bits may be set (enabled) or reset (disabled) by writing to the
register. Reading this register sets (enables) all bits to their
default ON condition.
The Scrambler_Enable bit enables operation of the SMPTE
scrambler function. This bit is normally ON.
The NRZI_Enable bit enables operation of the NRZ-to-NRZI
conversion function. This bit is normally ON.
The LSB_Clipping bit enables operation of the LSB clipping
function. This bit is normally ON.
The Sync_Detect_Enable bit enables operation of the TRS
detector function. This bit is normally ON.
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