DS92CK16_06 Datasheet, PDF(6/12 Page) National Semiconductor (TI) – 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

DS92CK16_06 Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

◁

Switching Characteristics (Continued)

Note 10: tSK1R is the difference in receiver propagation delay (|tPLHâtPHL|) of one device, and is the duty cycle distortion of the output at any given temperature and

VCC. The propagation delay specification is a device to device worst case over process, voltage and temperature.

Note 11: tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter

is guaranteed by design and characterization.

Note 12: tSK3R, part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. This specification

applies to devices over recommended operating temperature and voltage ranges, and across process distribution. TSK3R is defined as MaxâMin differential

propagation delay.This parameter is guaranteed by design and characterization.

Note 13: tSK1D is the difference in driver propagation delay (|tPLHâtPHL|) and is the duty cycle distortion of the CLKI/O outputs.

Note 14: tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This specification

applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK2D is defined as MaxâMin differential

propagation delay.

Note 15: Generator input conditions: tr/tf < 1 ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, VOL(max) 0.4V, VOH(min)

2.7V, Load = 7 pF (stray plus probes).

Parameter Measurement

Information

10108203

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

Generator waveform for all test unless otherwise specified: f = 25 MHz, 50% Duty Cycle, Zo = 50â¦, tTLH = 1 ns, tTHL = 1 ns.

10108204

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

www.national.com

FIGURE 3. Output Enable (OE) Delay Test Circuit

10108205

▷