DS92CK16_06 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 7, 8).
Symbol
Parameter
Conditions
Min
DIFFERENTIAL RECEIVER CHARACTERISTICS
t_PHLDR
Differential Propagation Delay High to Low. CLKI/O to C_L = 15 pF
1.3
CLK_OUT
VID = 250 mV
t_PLHDR
Differential Propagation Delay Low to High. CLKI/O to ^{Figures 1, 2}
1.3
CLK_OUT
t_SK1R
Duty Cycle Distortion(Note 10)
(pulse skew)
|t_PLH– t_PHL|
t_SK2R
Channel to Channel Skew; Same Edge (Note 11)
t_SK3R
Part to Part Skew (Note 12)
t_TLHR
Transition Time Low to High (Note 9)
0.4
(20% to 80% )
t_THLR
Transition Time High to Low(Note 9)
0.4
(80% to 20% )
t_PLHOER Propagation Delay Low to High
( OEto CLK_OUT)
t_PHLOER Propagation Delay High to Low
(OE to CLK_OUT)
f_MAX
Maximum Operating Frequency (Note 15)
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
C_L = 15 pF
1.0
Figures 3, 4
1.0
100
t_PHLDD
Differential Propagation Delay High to Low. CrdCLK_IN to C_L = 15 pF
0.5
CLKI/O
R_L = 37.5Ω
t_PLHDD
Differential Propagation Delay Low to High. CrdCLK_IN to ^{Figures 6, 7}
0.5
CLKI/O
t_PHLCrd
CrdCLK_IN to CLK_OUT Propagation Delay High to Low C_L = 15 pF
2.0
t_PLHCrd
CrdCLK_IN to CLK_OUT Propagation Delay Low to High ^{Figures 8, 9}
2.0
t_SK1D
Duty Cycle Distortion (pulse skew)
|t_PLH–t_PHL| (Note 13)
t_SK2D
Differential Part-to-Part Skew (Note 14)
t_TLHD
Differential Transition Time (Note 9)
0.4
(20% to 80% )
t_THLD
Differential Transition Time (Note 9)
0.4
(80% to 20% )
t_PHZD
t_PLZD
t_PZHD
t_PZLD
Transition Time High to TRI-STATE. DE to CLKI/O
Transition Time Low to TRI-STATE. DE to CLKI/O
Transition Time TRI-STATE to High. DE to CLKI/O
Transition Time TRI-STATE to Low. DE to CLKI/O
V_IN = 0V to V_CC
C_L = 15 pF,
R_L = 37.5Ω
Figures 10, 11
f_MAX
Maximum Operating Frequency (Note 15)
100
Typ
2.8
2.9
100
30
1.4
1.3
3
3
125
1.8
1.8
4.5
4.5
0.75
0.75
125
Max Units
3.8
ns
3.8
ns
400
ps
80
ps
2.5
ns
2.4
ns
2.2
ns
4.5
ns
4.5
ns
MHz
2.5
ns
2.5
ns
6.0
ns
6.0
ns
600
ps
2.0
ns
1.4
ns
1.4
ns
10
ns
10
ns
32
ns
32
ns
MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the
devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: ESD Rating: ESD qualification is performed per the following: HBM (1.5 kΩ, 100 pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC pins connected
together, all ground pins connected together.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD,
VTH, and VTL.
Note 4: All typicals are given for: V_CC = +3.3V and T_A = +25˚C.
Note 5: The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |V_CC–0V| may be applied between the
CLKI/O+ and CLKI/O− inputs, with the Common Mode set to V_CC/2.
Note 6: Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
Note 7: C_L includes probe and fixture capacitance.
Note 8: Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50Ω, t_r = 1 ns, t_f = 1 ns (10%–90%). To ensure fastest propagation delay and
minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V. In general, the faster the input edge rate, the better
the AC performance.
Note 9: All device output transition times are based on characterization measurements and are guaranteed by design.
5
www.national.com