DS92CK16_06 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

April 2006
DS92CK16
3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
General Description
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one
to six CMOS differential clock distribution device utilizing Bus
Low Voltage Differential Signaling (BLVDS) technology. This
clock distribution device is designed for applications requir-
ing ultra low power dissipation, low noise, and high data
rates. The BLVDS side is a transceiver with a separate
channel acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical) differential
input levels, and translates them to 3V CMOS output levels.
An output enable pin OE , when high, forces all CLK_OUT pins
high.
The device can be used as a source synchronous driver. The
selection of the source driving is controlled by the CrdCLK_IN
and DE pins. This device can be the master clock, driving the
inputs of other clock I/O pins in a multipoint environment.
Easy master/slave clock selection is achieved along a back-
plane.
Features
n Master/Slave clock selection in a backplane application
n 125 MHz operation (typical)
n 100 ps duty cycle distortion (typical)
n 50 ps channel to channel skew (typical)
n 3.3V power supply design
n Glitch-free power on at CLKI/O pins
n Low Power design (20 mA @ 3.3V static)
n Accepts small swing (300 mV typical) differential signal
levels
n Industrial temperature operating range (-40˚C to +85˚C)
n Available in 24-pin TSSOP Packaging
Function Diagram and Truth Table
Receive Mode Truth Table
INPUT
OUTPUT
OE DE CrdCLK_IN (CLKI/O+)–(CLKI/O−) CLK_OUT
HH
X
X
H
LH
X
VID≥ 0.07V
H
LH
X
VID≤ −0.07V
L
L = Low Logic State
H = High Logic State
X = Irrelevant
Z = TRI-STATE
10108201
Driver Mode Truth Table
INPUT
OUTPUT
OE DE CrdCLK_IN CLK/I/O+ CLKI/O− CLK_OUT
LL
L
L
H
L
LL
H
H
L
H
HL
L
L
H
H
HL
H
H
L
H
HH
X
Z
Z
H
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© 2006 National Semiconductor Corporation DS101082
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