DS90LV110AT Datasheet, PDF (6/9 Pages) National Semiconductor (TI) – 1 to 10 LVDS Data/Clock Distributor with Failsafe

DS90LV110A Pin Descriptions
Pin Name
IN+
IN -
OUT+
OUT -
EN
# of Pin
1
1
10
10
1
Input/Output
I
I
O
O
I
V_SS
3
P
V_DD
2
P
Application Information
INPUT FAIL-SAFE
The receiver inputs of the DS90LV110A have internal fail-
safe biasing for short, open, and teminated input conditions.
LVDS INPUTS TERMINATION
The LVDS Receiver input must have a 100Ω termination
resistor placed as close as possible across the input pins.
UNUSED CONTROL INPUTS
The EN control input pin has internal pull down device. If left
open, the 10 outputs will default to TRI-STATE.
EXPANDING THE NUMBER OF OUTPUT PORTS
To expand the number of output ports, more than one
DS90LV110A can be used. Total propagation delay through
the devices should be considered to determine the maxi-
mum expansion. Adding more devices will increase the out-
put jitter due to each pass.
PCB LAYOUT AND POWER SYSTEM BYPASS
Circuit board layout and stack-up for the DS90LV110A
should be designed to provide noise-free power to the de-
vice. Good layout practice also will separate high frequency
or high level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics
(4 to 10 mils) for power/ground sandwiches. This increases
the intrinsic capacitance of the PCB power system which
improves power supply filtering, especially at high frequen-
Description
Non-inverting LVDS input
Inverting LVDS input
Non-inverting LVDS Output
Inverting LVDS Output
This pin has an internal pull-down when left open. A
logic low on the Enable puts all the LVDS outputs into
TRI-STATE and reduces the supply current.
Ground (all ground pins must be tied to the same
supply)
Power Supply (all power pins must be tied to the same
supply)
cies, and makes the value and placement of external bypass
capacitors less critical. External bypass capacitors should
include both RF ceramic and tantalum electrolytic types. RF
capacitors may use values in the range 0.01 µF to 0.1 µF.
Tantalum capacitors may be in the range 2.2 µF to 10 µF.
Voltage rating for tantalum capacitors should be at least 5X
the power supply voltage being used. It is recommended
practice to use two vias at each power pin of the
DS90LV110A as well as all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half,
thereby reducing interconnect inductance and extending the
effective frequency range of the bypass components.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and iso-
lation as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity on signal transmission lines by providing
short paths for image currents which reduces signal distor-
tion. The planes should be pulled back from all transmission
lines and component mounting pads a distance equal to the
width of the widest transmission line or the thickness of the
dielectric separating the transmission line from the internal
power or ground plane(s) whichever is greater. Doing so
minimizes effects on transmission line impedances and re-
duces unwanted parasitic capacitances at component
mounting pads.
There are more common practices which should be followed
when designing PCBs for LVDS signaling. Please see Appli-
cation Note: AN-1108 for additional information.
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