DS90LV110AT Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – 1 to 10 LVDS Data/Clock Distributor with Failsafe

October 2004
DS90LV110AT
1 to 10 LVDS Data/Clock Distributor with Failsafe
General Description
DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS
(Low Voltage Differential Signaling) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The design allows connection of 1 input to
all 10 outputs. LVDS I/O enable high speed data transmis-
sion for point-to-point interconnects. This device can be used
as a high speed differential 1 to 10 signal distribution / fanout
replacing multi-drop bus applications for higher speed links
with improved signal quality. It can also be used for clock
distribution up to 200MHz.
The DS90LV110A accepts LVDS signal levels, LVPECL lev-
els directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE by use of the
enable pin.
For more details, please refer to the Application Information
section of this datasheet.
Features
n Low jitter 400 Mbps fully differential data path
n 145 ps (typ) of pk-pk jitter with PRBS = 2²³âˆ’1 data
pattern at 400 Mbps
n Single +3.3 V Supply
n Balanced output impedance
n Output channel-to-channel skew is 35ps (typ)
n Differential output voltage (V_OD) is 320mV (typ) with
100Ω termination load.
n LVDS receiver inputs accept LVPECL signals
n LVDS input failsafe
n Fast propagation delay of 2.8 ns (typ)
n Receiver open, shorted, and terminated input failsafe
n 28 lead TSSOP package
n Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
Block Diagram
20098205
Order Number DS90LV110ATMT
See NS Package Number MTC28
© 2004 National Semiconductor Corporation DS200982
20098201
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