DS90LV110AT Datasheet, PDF (3/9 Pages) National Semiconductor (TI) – 1 to 10 LVDS Data/Clock Distributor with Failsafe

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Units
SUPPLY CURRENT
I_CCD
Total Supply Current
R_L = 100Ω, C_L = 5 pF, 200 MHz,
EN = High
125 160 mA
No Load, 200 MHz, EN = High
80
125 mA
I_CCZ
TRI-STATE Supply Current
EN = Low
15
29
mA
Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All typical are given for V_CC = +3.3V and T_A = +25˚C, unless otherwise stated.
Note 3: V_OS is defined as (V_OH + V_OL) / 2.
Note 4: Only one output can be shorted at a time. Don’t exceed the package absolute maximum rating.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
T_LHT
Output Low-to-High Transition Time, 20% to 80%, Figure 4
(Note 5)
390 550
ps
T_HLT
T_DJ
T_RJ
Output High-to-Low Transition Time, 80% to 20%, Figure 4
(Note 5)
LVDS Data Jitter, Deterministic
(Peak-to-Peak)(Note 6)
V_ID = 300mV; PRBS=2²³-1 data;
V_CM = 1.2V at 400 Mbps (NRZ)
LVDS Clock Jitter, Random (Note 6)
V_ID = 300mV; V_CM = 1.2V
at 200 MHz clock
390 550
ps
145
ps
2.8
ps
T_PLHD
T_PHLD
T_SKEW
T_CCS
T_PHZ
T_PLZ
T_PZH
T_PZL
Propagation Low to High Delay, Figure 5
Propagation High to Low Delay, Figure 5
Pulse Skew |T_PLHD - T_PHLD| (Note 5)
Output Channel-to-Channel Skew, Figure 6 (Note 5)
Disable Time (Active to TRI-STATE) High to Z, Figure 1
Disable Time (Active to TRI-STATE) Low to Z, Figure 1
Enable Time (TRI-STATE to Active) Z to High, Figure 1
Enable Time (TRI-STATE to Active) Z to Low, Figure 1
2.2
2.8
3.6
ns
2.2
2.8
3.9
ns
20
340
ps
35
91
ps
3.0
6.0
ns
1.8
6.0
ns
10.0 23.0
ns
7.0 23.0
ns
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 6: The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and
HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a T_DJ = 26ps and T_RJ = 1.3 ps
3
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