ADC08500_09 Datasheet, PDF (6/34 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

Pin Functions
Pin No.
Symbol
79
OR+
80
OR-
82
DCLK+
81
DCLK-
2, 5, 8, 13,
16, 17, 20,
25, 28, 33,
128
40, 51 ,62,
73, 88, 99,
110, 121
1, 6, 9, 12,
21, 24, 27,
41
42, 53, 64,
74, 87, 97,
108, 119
22, 23, 29,
36–39,
43–50, 52,
54–61, 63,
65–72,
75–78, 98,
109, 120
V_A
V_DR
GND
DR GND
NC
Equivalent Circuit
Description
Out Of Range output. A differential high at these pins indicates
that the differential input is out of range (outside the range
±V_IN/2 as programmed by the FSR pin in non-extended control
mode or the Input Full-Scale Voltage Adjust register setting in
the extended control mode).
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input clock
rate in SDR mode and at 1/4 the input clock rate in the DDR
mode. The DCLK outputs are not active during a calibration
cycle, therefore this is not recommended as a system clock.
Analog power supply pins. Bypass these pins to ground.
Output Driver power supply pins. Bypass these pins to DR
GND.
Ground return for V_A.
Ground return for V_DR.
No Connection. Make no connection to these pins.
www.national.com
6