ADC08500_09 Datasheet, PDF (28/34 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

that (100Ω) characteristic impedance. The clock line should
be as short and as direct as possible. The ADC08500 clock
input is internally terminated with an untrimmed 100Ω resis-
tor.
Insufficient clock levels will result in poor dynamic perfor-
mance. Excessively high clock levels could cause a change
in the analog input offset voltage. To avoid these problems,
keep the clock level within the range specified as V_ID in the
Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08500 features
a duty cycle clock correction circuit which can maintain per-
formance over temperature. The ADC will meet its perfor-
mance specification if the input clock high and low times are
maintained within the duty cycle range as specified in the
Converter Electrical Characteristics.
High speed, high performance ADCs such as the ADC08500
require a very stable clock signal with minimum phase noise
or jitter. ADC jitter requirements are defined by the ADC res-
olution (number of bits), maximum ADC input frequency and
the input signal amplitude relative to the ADC input full scale
range. The maximum jitter (the sum of the jitter from all
sources) allowed to prevent a jitter-induced reduction in SNR
is found to be
t_J(MAX) = (V_IN(P-P) / V_INFSR) x (1/(2^(N+1) x π x f_IN))
where t_J(MAX) is the rms total of all jitter sources in seconds,
V_IN(P-P) is the peak-to-peak analog input signal, V_INFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and f_IN is the maximum input frequency, in Hertz, at the ADC
analog input.
Note that the maximum jitter described above is the RSS sum
of the jitter from all sources, including that in the ADC clock,
that added by the system to the ADC clock and input signals
and that added by the ADC itself. Since the effective jitter
added by the ADC is beyond user control, the best the user
can do is to keep the sum of the externally added clock jitter
and the jitter added by the analog circuitry to the analog signal
to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the ADC08500
and facilitate its use. These control pins provide Full-Scale
Input Range setting, Self Calibration, Calibration Delay, Out-
put Edge Synchronization choice, LVDS Output Level choice
and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR con-
trol input (pin 14) in the normal mode of operation. The is
specified as V_IN in the Converter Electrical Characteristics. In
the extended control mode, the input full-scale range may be
programmed using the Full-Scale Adjust Voltage register.
See 2.2 THE ANALOG INPUT for more information.
2.4.2 Self Calibration
The ADC08500 self-calibration must be run to achieve spec-
ified performance. The calibration procedure is run upon pow-
er-up and can be run any time on command. The calibration
procedure is exactly the same whether there is a clock
present upon power up or if the clock begins some time after
application of power. The CalRun output indicator is high
while a calibration is in progress.
It is important that no digital activity take place on any of the
digital input lines during the calibration process, except that
there must be a stable, constant frequency CLK signal
present and that SCLK may be active if the Enhanced Mode
is selected. Specifically, none of the following actions are al-
lowed during the calibration process:
✓ Changing OUTV
✓ Changing OutEdge or SDATA sense
✓ Changing between SDR and DDR
✓ Changing FSE or ECE
✓ Changing DCLK_RST
✓ Changing SCS
✓ Raising PD high
✓ Raising CAL high
Doing any of these actions can cause faulty calibration.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08500 will function with the CAL pin held high
at power up, but no calibration will be done and performance
will be impaired. A manual calibration, however, may be per-
formed after powering up with the CAL pin high. See 2.4.2.2
On-Command Calibration.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the clock is not running at power up and
the power on calibration circuitry is active, it will hold the ana-
log circuitry in power down and the power consumption will
typically be less than 200 mW. The power consumption will
be normal after the clock starts.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high
for a minimum of t_{CAL_H} input clock cycles after it has been
low for a minimum of t_{CAL_L} input clock cycles. Holding the
CAL pin high upon power up will prevent execution of power-
on calibration until the CAL pin is low for a minimum of
t_{CAL_L} input clock cycles, then brought high for a minimum of
another t_{CAL_H} input clock cycles. The calibration cycle will
begin t_{CAL_H} input clock cycles after the CAL pin is thus
brought high. The CalRun signal should be monitored to de-
termine when the calibration cycle has completed.
The minimum t_{CAL_H} and t_{CAL_L} input clock cycle sequences
are required to ensure that random noise does not cause a
calibration to begin when it is not desired. As mentioned in
1.1.1 Self-Calibration for best performance, a self calibration
should be performed 20 seconds or more after power up and
repeated when the operating temperature changes signifi-
cantly according to the particular system performance re-
quirements. ENOB drops slightly as junction temperature
increases and executing a new self calibration cycle will es-
sentially eliminate the change.
During a Power-On calibration cycle, both the ADC and the
input termination resistor are calibrated. As dynamic perfor-
mance changes slightly with junction temperature, an On-
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