ADC08500_09 Datasheet, PDF (23/34 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

TABLE 1. Features and Modes
Feature
Normal Control Mode
Extended Control Mode
SDR or DDR Clocking
DDR Clocking selected with pin 4
floating. SDR clocking selected when pin
4 not floating.
Selected with nDE in the Configuration
Register (Addr-1h; bit-10). When the
device is in DDR mode, address 1h, bit-8
must be set to 0b.
DDR Clock Phase
Not Selectable (0° Phase Only)
Selected with DCP in the Configuration
Register (Addr- 1h; bit-11).
SDR Data transitions with rising or falling
DCLK edge
SDR Data transitions with rising edge of
DCLK+ when pin 4 is high and on falling
edge when low.
Selected with OE in the Configuration
Register (Addr- 1h; bit-8).
LVDS output level
Normal differential data and DCLK
amplitude selected when pin 3 is high
and reduced amplitude selected when
low.
Selected with the OV in the
Configuration Register (Addr- 1h; bit-9).
Power-On Calibration Delay
Short delay selected when pin 127 is low
and longer delay selected when high.
Short delay only.
Full-Scale Range
Normal input full-scale range selected ^{Up to 512 step adjustments over a}
when pin 14 is high and reduced range
nominal range specified in 1.4
REGISTER DESCRIPTION. Selected
when low. Selected range applies to both
channels.
using the Input Full-Scale Adjust register
(Addr- 3h; bits-7 thru 15).
Input Offset Adjust
Not possible
512 steps of adjustment using the Input
Offset register (Addr- 2h; bits-7 thru 15)
as specified in 1.4 REGISTER
DESCRIPTION.
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 2.
TABLE 2. Extended Control Mode Operation
(Pin 14 Floating)
Feature
Extended Control Mode
Default State
SDR or DDR Clocking
DDR Clocking
DDR Clock Phase
Data changes with DCLK
edge (0° phase)
LVDS Output Amplitude
Calibration Delay
Normal amplitude
(710 mV_P-P)
Short Delay
Full-Scale Range
700 mV nominal for both
channels
Input Offset Adjust
No adjustment for either
channel
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial
interface, all 3 user registers must be written with desired or
default values. Once all registers have been written once,
other desired settings can be loaded.
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS). Three write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of this
signal. There is no minimum frequency requirement for SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See Figure 5.
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 3.
Refer to 1.4 REGISTER DESCRIPTION for information on
the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
IMPORTANT NOTE: The Serial Interface should not be writ-
ten to when calibrating the ADC. Doing so will impair the
performance of the device until it is re-calibrated correctly.
Programming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register access
time.
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