ADC08500_09 Datasheet, PDF (27/34 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

lected to aid in designing the best performing single-ended to
differential conversion circuit using that particular balun.
When selecting a balun, it is important to understand the input
architecture of the ADC. There are specific balun parameters
of which the system designer should be mindful. A designer
should match the impedance of their analog source to the
ADC08500's on-chip 100Ω differential input termination re-
sistor. The range of this input termination resistor is described
in the electrical table as the specification R_IN.
Also, the phase and amplitude balance are important. The
lowest possible phase and amplitude imbalance is desired
when selecting a balun. The phase imbalance should be no
more than ±2.5° and the amplitude imbalance should be lim-
ited to less than 1dB at the desired input frequency range.
Finally, when selecting a balun, the VSWR (Voltage Standing
Wave Ratio), bandwidth and insertion loss of the balun should
also be considered. The VSWR aids in determining the overall
transmission line termination capability of the balun when in-
terfacing to the ADC input. The insertion loss should be
considered so that the signal at the balun output is within the
specified input range of the ADC as described in the Con-
verter Electrical Characteristics as the specification V_IN.
2.2.1.2 d.c. Coupled Input
When d.c. coupling to the ADC08500 analog inputs is re-
quired, single-ended to differential conversion may be easily
accomplished with the LMH6555. An example of this type of
circuit is shown in Figure 13. In such applications, the
LMH6555 performs the task of single-ended to differential
conversion while delivering low distortion and noise, as well
as output balance, that supports the operation of the
ADC08500. Connecting the ADC08500 V_CMO pin to the
V_{CM_REF} pin of the LMH6555, through an appropriate buffer,
will ensure that the common mode input voltage is as needed
for optimum performance of the ADC08500. The LMV321
was chosen to buffer V_CMO for its low voltage operation and
reasonable offset voltage.
Be sure that the current drawn from the V_CMO output does not
exceed 100 μA.
TABLE 5. D.C. Coupled Offset Adjustment
Unadjusted Offset
Reading
Resistor Value
0mV to 10mV
no resistor needed
11mV to 30mV
20.0kΩ
31mV to 50mV
10.0kΩ
51mV to 70mV
6.81kΩ
71mV to 90mV
4.75kΩ
91mV to 110mV
3.92kΩ
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh.
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08500 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08500 such that the differential full-scale input
range at the analog inputs is a normal amplitude with the FSR
pin high, or a reduced amplitude with FSR pin low as defined
by the specification V_IN in the Converter Electrical Character-
istics. Best SNR is obtained with FSR high, but better distor-
tion and SFDR are obtained with the FSR pin low.
2.3 THE CLOCK INPUTS
The ADC08500 has differential LVDS clock inputs, CLK+ and
CLK-, which must be driven with an a.c. coupled, differential
clock signal. Although the ADC08500 is tested and its perfor-
mance is guaranteed with a differential 500 MHz clock, it
typically will function well with clock frequencies indicated in
the Converter Electrical Characteristics. The clock inputs are
internally terminated and biased. The clock signal must be
capacitively coupled to the clock pins as indicated in Figure
14.
Operation up to the sample rates indicated in the Converter
Electrical Characteristics is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and prod-
uct lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management . See 2.6.2 Thermal
Management.
20206455
FIGURE 13. Example of Servicing the Analog Input with
V_CMO
In Figure 13, R_ADJ- and R_ADJ+ are used to adjust the differential
offset that can be measured at the ADC inputs V_IN+ / V_IN-. An
unadjusted positive offset with reference to V_IN- greater than
|15mV| should be reduced with a resistor in the R_ADJ- position.
Likewise, an unadjusted negative offset with reference to
V_IN- greater than |15mV| should be reduced with a resistor in
the R_ADJ+ position. Table 5 gives suggested R_ADJ- and R_ADJ+
values for various unadjusted differential offsets to bring the
V_IN+ / V_IN- offset back to within |15mV|.
20206447
FIGURE 14. Differential (LVDS) Clock Connection
The differential Clock line pair should have a characteristic
impedance of 100Ω and be terminated at the clock source in
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