PC87391 Datasheet, PDF (56/148 Pages) National Semiconductor (TI) – 100-Pin LPC SuperI/O Devices for Portable Applications

2.0 Device Architecture and Configuration (Continued)
2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION
This section applies to the PC87392, PC87393 and PC87393F only.
2.15.1 General Description
The GPIO functional block includes 32 pins, arranged in four 8-bit ports (ports 0, 1, 2 and 3). All pins in ports 0 and 1 are
I/O, and have full event detection capability, enabling them to trigger the assertion of IRQ and SMI signals. Pins in ports 2
and 3 are I/O, but none of them has event detection capability. The twelve runtime registers associated with the four ports
are arranged in the GPIO address space as shown in Table 23. The GPIO base address is 16-byte aligned. Address bits 3-
0 are used to indicate the register offset.
Table 23. Runtime Registers in GPIO Address Space
Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
Mnemonic
Register Name
GPDO0 GPIO Data Out 0
GPDI0 GPIO Data In 0
GPEVEN0 GPIO Event Enable 0
GPEVST0 GPIO Event Status 0
GPDO1 GPIO Data Out 1
GPDI1 GPIO Data In 1
GPEVEN1 GPIO Event Enable 1
GPEVST1 GPIO Event Status 1
GPDO2 Data Out 2
GPDI2 Data In 2
GPDO3 Data Out 3
GPDI3 Data In 3
Port Type
0 R/W
RO
R/W
R/W1C
1 R/W
RO
R/W
R/W1C
2 R/W
RO
3 R/W
RO
2.15.2 Implementation
The standard GPIO port with event detection capability (such as ports 0 and 1) has four runtime registers. Each pin is asso-
ciated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard ports
that do not support event detection, and therefore differ from the generic model as follows:
q _{They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers}
GPEVEN2/3 and GPEVST2/3 are not available.
q _{Only bits 3-0 are implemented in the GPIO Pin Configuration registers of ports 2 and 3. Bits 6-4, associated with the}
event detection functionality, are reserved.
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