PC87382 Datasheet, PDF (52/72 Pages) National Semiconductor (TI) – LPC-to-LPC Switch for Docking Stations, with Fast Infrared Port, Serial Port and GPIOs

7.0 Legacy Functional Blocks (Continued)
Bank UART Mode
0

1

2

3

4
5
6
7
Table 29. Register Bank Summary
IR Mode








Main Functions
Global Control and Status
Legacy Bank
Alternative Baud Generator Divisor, Extended Control and Status
Module Revision ID and Shadow registers
IR mode setup
IR Control and Status FIFO
IR Physical Layer Configuration
CEIR and Optical Transceiver Configuration
The register maps in this chapter use the following abbreviations for Type:
q _{R/W = Read/Write.}
q _{R = Read from a specific address returns the value of a specific register. Write to the same address is to a different}
register.
q _{W = Write.}
q _{RO = Read Only.}
q _{R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.}
7.2.3 IR Register Map for IR Functionality
Table 30. Bank 0 Register Map
Offset
00h
01h
02h
03h
04h
05h
06h
07h
Mnemonic
Register Name
RXD
TXD
IER
Receiver Data
Transmitter Data
Interrupt Enable
EIR
FCR
LCR
Event Identification
FIFO Control
Link Control
BSR
MCR
LSR
Bank Select
Modem / Mode Control
Link Status
MSR
SPR
ASCR
Modem Status
Scratch Pad
Auxiliary Status and Control
Type
RO
W
R/W
R
W
W
R/W
R/W
R/W
R
R/W
Varies per bit
Table 31. Bank 1 Register Map
Offset Mnemonic
Register Name
00h
LBGD(L)
01h
LBGD(H)
02h
03h LCR/BSR
04h - 07h
Legacy Baud Generator Divisor (Low Byte)
Legacy Baud Generator Divisor (High Byte)
Reserved
Link Control / Bank Select
Reserved
Type
R/W
R/W
R/W
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