PC87382 Datasheet, PDF (27/72 Pages) National Semiconductor (TI) – LPC-to-LPC Switch for Docking Stations, with Fast Infrared Port, Serial Port and GPIOs

3.0 Device Architecture and Configuration (Continued)
3.7.2 SuperI/O Configuration 1 Register (SIOCF1)
Location: Index 21h
Type: Varies per bit
Bit
Name
Reset
7
6
LOCKMCF LOCKGCF
0
0
5
4
Reserved
0
1
3
2
IOWAIT
0
0
1
Reserved
0
0
GLOBEN
1
Bit Type
Description
7 R/W1S LOCKMCF (Lock Multiplexing Configuration). When set to 1, this bit locks the configuration of
registers SIOCF1 and SIOCF2 by disabling writing to all bits in these registers (including the LOCKMCF
bit itself), except for the LOCKGCF and GLOBEN bits in SIOCF1. Once set, this bit can only be cleared
by Hardware reset.
0: R/W bits are enabled for write (default).
1: All bits are RO.
6 R/W1S LOCKGCF (Lock GPIO Pins Configuration). When set to 1, this bit locks the configuration registers
of all GPIO pins (see Section 3.10.3 on page 33) by disabling writes to all their bits (including the
LOCKGCF bit itself). The locked registers include the GPCFG (except LOCKCFP bit) and GPEVR
registers of all GPIO pins. Once set, this bit can only be cleared by Hardware reset.
0: R/W bits are enabled for write (default).
1: All bits are RO.
5-4
Reserved. These bits must be ‘01’.
3-2 R/W or IOWAIT (Number of I/O Wait States). These bits set the number of wait states for I/O transactions
RO through the LPC bus.
Bits
3 2 Number of Wait States
0 0: 0 (default)
0 1: 2
1 0: 6
1 1: 12
1
Reserved. This bit must be 0.
0 R/W or GLOBEN (Global Device Enable). This bit makes it possible to disable all logical devices by setting a
RO single bit (to 0). In addition, when the bit is set to 1, it enables the operation of all the logical devices
of the PC87382, as long as the logical device is itself enabled (see Table 7 on page 19). The behavior
of the different devices is explained in Section 3.3 on page 24.
0: All logical devices in the PC87382 are disabled and their resources are released.
1: Enables each PC87382 logical device that is itself enabled (default); see Section 3.3.1 on page 24.
3.7.3 SuperI/O Configuration 2 Register (SIOCF2)
This register is reset by hardware to 63h.
Location: Index 22h
Type: R/W or RO
This register is reserved. It must be written with 63h
Revision 1.2
27
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