DS99R421_08 Datasheet, PDF (5/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Input Timing Requirements for OS[2:0]
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
F_OS[2:0]
Maximum Frequency
Limitation of OS[2:0]
OS[2:0]
F_RxCLKIN / 5
MHz
Input to Output Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
RCTCD
RxCLK IN to DOUT Delay
(Figure 5), (Note 9)
5 MHz–43 MHz _{4T + 1.0}
PDD
Power Down Delay
5 MHz–43 MHz
Typ
4T + 5.0
Max
4T + 10.0
1
Units
ns
µs
Serializer Output Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
t_LLHT
t_LHLT
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
R_T = 100Ω,
C_L = 10 pF to GND
(Figure 4)
0.3
0.5
0.3
0.5
t_PLT
PLL Lock Time
5 MHz–43 MHz
10
TxOUT_E_O TxOUT_Eye_Opening
(Notes 8, 11) (Figure 9)
5 MHz–43 MHz
(respect to ideal)
0.78
UI
Unit Interval
(Note 8)
5 MHz–43 MHz
1/28th of
DOUT
Units
ns
ns
ms
UI
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD, ΔV_OD,
V_TH and V_TL which are differential voltages.
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: Specification is guaranteed by design and is not tested in production.
Note 7: Total Interconnect Jitter Budget (t_JIT) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are SerDes circuits.
Note 8: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
For the input, it is 1/7th the input clock period. Example 43 MHz = 23.26 ns. 1/7th of this is 3.32 ns. This is 1 UI of the input at 43 MHz.
For the output, it is 1/28th of the input clock period. Example 43 MHz = 23.26 ns. 1/28th of this is 831 ps. This is 1 UI of the output at 43 MHz.
Note 9: A Clock Unit Symbol (T) is defined as 1/ (Line rate of RxCLKIN).
Note 10: Receiver Input Tolerance is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window – RSPos). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter.
Note 11: TxOUT_E_O is affected by pre-emphasis value.
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