DS99R421_08 Datasheet, PDF (4/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Symbol
Parameter
Conditions
Pin/Freq.
Min
V_OD
Output Differential Voltage R_T = 100Ω
(Figure 10)
VODSEL = L
LVDS differential Outputs:
DOUT±
380
R_T = 100Ω
650
VODSEL = H
ΔV_OD
Output Differential Voltage R_T = 100Ω
Unbalance
V_OS
Output Voltage Offset
R_T = 100Ω
1.0
PRE = H (off)
ΔV_OS
Output Voltage Offset
Difference
R_T = 100Ω
PRE = H (off)
I_OS
Output Short Circuit
DOUT± = 0V
Current
VODSEL = L
−2
PRE = H (off)
DOUT± = 0V
VODSEL = H
−7
PRE = H (off)
I_OZ
TRI-STATE Output Current PWDNB = 0V,
DOUT± = 0V OR V_DD
−10
(inputs not toggling)
R_T
Internal Input Termination
Resistance
RxIN:
across RxIN(2:0)+ & RxIN
(2:0)−, and across
90
RxCLKIN+ & RxCLKIN−
CONVERTER SUPPLY CURRENT
I_DD
Total Supply Current
R_T = 100Ω
f = 43 MHz
(includes load current)
CHECKERBOARD pattern
PRE = 6 KΩ (Figure 3)
I_DDTZ
Supply Current Power-
down
PWDNB = 0V
(inputs not toggling)
Typ Max Units
500
630 mV
900 1150 mV
10
50
mV
1.2
1.5
V
5
50
mV
−8
mA
−13 mA
±1
+10 µA
105
130
Ω
95
130 mA
2
50
µA
Receiver Input Timing Requirements
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_RCIH
Receiver Clock Input High Time
Referenced to rising edge of
RxCLKIN
t_RCIL
Receiver Clock Input Low Time
Referenced to rising edge of
RxCLKIN
Min
0.35T
Typ
0.57T
0.43T
Max
0.65T
Units
ns
ns
Receiver Input Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
RITOL-L
Receiver Input Tolerance Left
(Figures 7, 8) (Notes 8, 10)
5 MHz–43 MHz
0.3
RITOL-R
Receiver Input Tolerance
5 MHz–43 MHz
Right
0.3
(Figures 7, 8) (Notes 8, 10)
UI
Unit Interval
(Note 8)
5 MHz–43 MHz
1/7th of
RxCLKIN
Units
UI
UI
ns
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