DS99R421_08 Datasheet, PDF (11/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Functional Description
The DS99R421 is a Video Interface converter. It converts an
FPD-Link interface (3 LVDS data channels + 1 LVDS Clock,
e.g. DS90C365A or equivalent) plus up to three (3) LVCMOS
additional signals into a single high-speed LVDS serial Inter-
face (see Figure 11).
The 21 bits of data from the FPD-Link Interface are serialized
along with the 3 additional over-sampled bits (OS[2:0]) into a
randomized, scrambled and DC Balanced data stream to
support AC coupling and to enhance the signal eye opening.
Four (4) additional overhead bits are sent per clock which
provides the embedded clock and serial link control informa-
tion. The embedded clock LVDS serial stream has an effec-
tive data throughput of 120 Mbps (5MHz X 24) to 1.03 Gbps
(43MHz X 24). The DS99R421 Line Driver is designed to
transmit data up to 10 meters over shielded twisted pair (STP)
at signaling rates up to 1.2Gbps (43MHz X 28).
The DS90UR124 receiver converts the embedded clock
LVDS stream back into a 24-bit wide LVCMOS parallel bus
and the recovered low-speed clock.
Note: The DS90C124 is not compatible with the DS99R421.
LINK START UP
The start up of the DS99R421 involves only one PLL Lock
time. The FPD-Link Receiver side must lock to its incoming
LVDS RxCLKIN. The Serializer side then extracts its refer-
ence clock from the incoming LVDS clock. At the far end of
the link, the Deserializer (DS90UR124) also needs to detect
the LVDS signals and lock to the incoming serial stream,
drives the LOCK pin HIGH, before outputting valid data. Note
that when using a Bus Converter (FPD-Link to Serial) addi-
tional time is required in the start up to account for the addi-
tional PLLs in the path.
TYPICAL START UP SEQUENCE
1. FPD-Link Stream is applied to the DS99R421 inputs.
2. With power applied and the DS99R421 enabled, it will
lock to the incoming FPD-Link clock. Until the DS99R421
is ready, it will hold its outputs in TRI-STATE. Once the
locking is complete, valid serial payloads are sent across
the link to the DES (DS90UR124).
3. With power applied and the device enabled, the
DS90UR124 will lock to the incoming serial stream. Until
the DS90UR124 is locked, outputs are in TRI-STATE
and its LOCK output pin is held Low. After Lock, the
DS90UR124 outputs are active and LOCK is HIGH.
DATA TRANSFER
After the link start up, the DS99R421 provides a streaming
video interface. For each Pixel Clock (PCLK) received from
the FPD-Link Interface 21 bits of information are recovered
along with the PCLK. The 21 bits of information include the
18-bits of RGB information and the three video control signals
(HS, VS and DE). The over-sample control bits are also sam-
pled in this PCLK domain and appended to the 21 bits of
information for a 24-bit total payload. The Serializer side now
takes this data and performs four operations to it. First the
data is randomized, second the data is scrambled, third the
data is balanced, and finally the serial link control and clock
embedding is done. The Serializer transmits 28 bits of infor-
mation per payload to the Deserializer per PCLK. See
DS90UR241 datasheet for additional information on the
Serializer’s description and operation.
The chipset supports PCLK frequency ranges of 5 MHz to 43
MHz. At the 43MHz PCLK rate, 28 bits are sent across the
serial link at 1.2Gbps. The link is very efficient, sending 25
bits of information (18 RGB, 3 control, 3 over-sample control,
and PCLK) with 28 serial bits. This yields 89% efficiency.
DS99R421 LINE DRIVER
The DS99R421 output (DOUT±) is used to drive a point-to-
point connection as shown in Figure 12. The Line driver
transmits data when the data enable pin (DEN) is HIGH, the
power down bar (PWDNB) is HIGH, and the device is locked
to the incoming FPD-Link stream. If the DEN is set LOW, the
device remains locked, but the driver outputs are placed in
TRI-STATE. This maybe used to provide a fast start up since
a lock time is not required.
PRE-EMPHASIS
The DS99R421 features a Pre-Emphasis function used to
compensate for extra long or lossy transmission media. Cable
drive is enhanced with a user selectable Pre-Emphasis fea-
ture that provides additional output current during transitions
to counteract cable loading effects. The transmission dis-
tance will be limited by the loss characteristics and quality of
the media.
To enable the Pre-Emphasis function, the “PRE” pin requires
one external resistor (Rpre) to Vss in order to set the addi-
tional current level. Options include:
Normal Output (no pre-emphasis) – Leave the PRE pin open
Enhanced Output (pre-emphasis enabled) – connect a resis-
tor on the PRE pin to Vss. Values of the PRE Resistor should
be between 6K Ohm and 100M Ohm. Values less than 6K
Ohm should not be used. The amount of Pre-Emphasis for a
given media will depend on the transmission distance and
Fmax of the application. In general, too much Pre-Emphasis
can cause over or undershoot at the receiver input pins. This
can result in excessive noise, crosstalk, reduced Fmax, and
increased power dissipation. For shorter cables or distances,
Pre-Emphasis is typically not be required. Signal quality mea-
surements should be made at the end of the application cable
to confirm the proper amount of Pre-Emphasis for the specific
application.
The Pre-Emphasis circuit increases the drive current to I =
48 / (Rpre). For example if Rpre = 15K Ohm, then the Pre-
Emphasis current is increased by an additional 3.2 mA.
The duration of the current is controlled to precisely one bit
by another circuit. If more than one bit value is repeated in the
next cycle(s), the next bit(s) is “de-emphasized”; Pre-Empha-
sis is turned off (back to the normal output current level, hence
output level is also reduced). This is done to reduce power,
and to reduce ISI (Inter-Symbol Interference).
VOD SELECT
The Serializer Line Driver Differential Output Voltage (VOD)
magnitude is selectable. Two levels are provided and are de-
termined by the state of the VODSEL pin. When this pin is
LOW, normal output levels are obtained. For most application
set the VODSEL pin LOW. When this pin is HIGH, the output
current is increased to increase the VOD level. Use this set-
ting only for extra long cable or high-loss interconnects.
OVER-SAMPLED BITS – OS[2:0]
Up to three additional signals maybe sent across the serial
link per PCLK. The over-sampled bits are restricted to be low
speed signals and should be less than 1/5 of the frequency of
the PCLK. The DS99R421 OS[2:0] LVCMOS Inputs have
wide hysteresis to help prevent glitches. Signals should con-
vey level information only, as pulse width distortion will occur
by the over sampling technique and location of the sampling
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