DS99R421_08 Datasheet, PDF (14/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Functional Overview
FPD-Link LVDS Input Mapping
(3 LVDS Data + 1 LVDS Clock)
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* Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC Balanced
Single Serialized LVDS Bitstream*
FIGURE 11. LVDS Data Mapping Diagram
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