DS90LV804 Datasheet, PDF (5/6 Pages) National Semiconductor (TI) – 4-Channel 800 Mbps LVDS Buffer/Repeater

Feature Descriptions
INTERNAL TERMINATIONS
The DS90LV804 has integrated termination resistors on both
the input and outputs. The inputs have a 100Ω resistor
across the differential pair, placing the receiver termination
as close as possible to the input stage of the device. The
LVDS outputs also contain an integrated 100Ω ohm termi-
nation resistor, this resistor is used to reduce the effects of
Near End Crosstalk (NEXT) and does not take the place of
the 100 ohm termination at the inputs to the receiving device.
The integrated terminations improve signal integrity and de-
crease the external component count resulting in space
savings.
OUTPUT CHARACTERISTICS
The output characteristics of the DS90LV804 have been
optimized for point-to-point backplane and cable applica-
tions, and are not intended for multipoint or multidrop signal-
ing.
TRI-STATE MODE
The EN input activates a hardware TRI-STATE mode. When
the TRI-STATE mode is active (EN=L), all input and output
buffers and internal bias circuitry are powered off and dis-
abled. Outputs are tri-stated in TRI-STATE mode. When
exiting TRI-STATE mode, there is a delay associated with
turning on bandgap references and input/output buffer cir-
cuits as indicated in the LVDS Output Switching Character-
istics
INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to
provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to V_DD thru a pull up resistor and the negative
LVDS input pin is tied to GND by a pull down resistor. The
pull up and pull down resistors should be in the 5kΩ to 15kΩ
range to minimize loading and waveform distortion to the
driver. The common-mode bias point ideally should be set to
approximately 1.2V (less than 1.75V) to be compatible with
the internal circuitry. Please refer to application note AN-
1194 “Failsafe Biasing of LVDS Interfaces” for more informa-
tion.
TYPICAL PERFORMANCE CHARACTERISTICS
20156741
Dynamic power supply current was measured while running a clock or
PRBS 2²³-1 pattern with all 4 channels active. V_CC = 3.3V, T_A = +25˚C,
V_ID = 0.5V, V_CM = 1.2V
Power Supply Current vs. Bit Data Rate
Packaging Information
The Leadless Leadframe Package (LLP) is a leadframe
based chip scale package (CSP) that may enhance chip
speed, reduce thermal impedance, and reduce the printed
circuit board area required for mounting. The small size and
very low profile make this package ideal for high density
PCBs used in small-scale electronic applications such as
cellular phones, pagers, and handheld PDAs. The LLP pack-
age is offered in the no Pullback configuration. In the no
Pullback configuration the standard solder pads extend and
terminate at the edge of the package. This feature offers a
visible solder fillet after board mounting.
The LLP has the following advantages:
• Low thermal resistance
• Reduced electrical parasitics
• Improved board space efficiency
• Reduced package height
• Reduced package mass
For more details about LLP packaging technology, refer to
applications note AN-1187, "Leadless Leadframe Package"
5
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