DS90LV804 Datasheet, PDF (4/6 Pages) National Semiconductor (TI) – 4-Channel 800 Mbps LVDS Buffer/Repeater

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V_OD
Differential Output Voltage
R_L = 100Ω external resistor between OUT+ and
(Note 6)
OUT−
∆V_OD
Change in V_OD between
Complementary States
V_OS
∆V_OS
Offset Voltage (Note 7)
Change in V_OS between
Complementary States
I_OS
Output Short Circuit Current
C_OUT2 Output Capacitance
SUPPLY CURRENT (Static)
OUT+ or OUT− Short to GND
OUT+ or OUT− to GND when TRI-STATE
I_CC
Total Supply Current
All inputs and outputs enabled and active,
terminated with external differential load of 100Ω
between OUT+ and OUT-.
I_CCZ
TRI-STATE Supply Current EN = 0V
SWITCHING CHARACTERISTICS — LVDS OUTPUTS
t_LHT
Differential Low to High
Transition Time
t_HLT
Differential High to Low
Transition Time
Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of V_OD.
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% V_OD between input to output.
t_SKD1
t_SKCC
Pulse Skew
Output Channel to Channel
Skew
|t_PLHD– t_PHLD|
Difference in propagation delay (t_PLHD or t_PHLD)
among all output channels.
t_JIT
Jitter
(Note 8)
RJ - Alternating 1 and 0 at 400 MHz (Note 9)
DJ - K28.5 Pattern, 800 Mbps (Note 10)
TJ - PRBS 2²³-1 Pattern, 800 Mbps (Note 11)
t_ON
LVDS Output Enable Time
Time from EN to OUT± change from
TRI-STATE to active.
t_OFF
LVDS Output Disable Time Time from EN to OUT± change from active to
TRI-STATE.
Min
250
−35
1.05
−35
Typ
Max
(Note 5)
500
600
35
1.18 1.475
35
−60 −90
5.5
117
140
2.7
6
210
300
210
300
2.0
3.2
2.0
3.2
25
80
50
125
1.1
1.5
15
35
30
55
300
12
Units
mV
mV
V
mV
mA
pF
mA
mA
ps
ps
ns
ns
ps
ps
psrms
psp-p
psp-p
ns
ns
Note 5: Typical parameters are measured at V_DD = 3.3V, T_A = 25˚C. They are for reference purposes, and are not production-tested.
Note 6: Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
Note 7: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50% duty cycle at 400
MHz, t_r = t_f = 50ps (20% to 80%).
Note 10: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V_ID = 500mV, K28.5 pattern at 800 Mbps,
t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage
= V_ID = 500mV, 2²³-1 PRBS pattern at 800 Mbps, t_r = t_f = 50ps (20% to 80%).
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